Semiconductor device having semiconductor chip with large and small irregularities on upper and lower side surface portions thereof

1. A semiconductor device, comprising:

a semiconductor chip having a bottom surface;

a die pad supporting the semiconductor chip;

an adhesive adhering the semiconductor chip and the die pad;

a plurality of signal leads extending toward a side of the die pad;

bonding wires connecting the semiconductor chip and the plurality of signal leads; and

an encapsulating body encapsulating the semiconductor chip, the bonding wires and a part of each signal lead with a mold resin,

wherein a side surface of the semiconductor chip comprises a first irregular side surface and a second irregular side surface located above the first irregular side surface,

wherein the first irregular side surface and the second irregular side surface are both generally perpendicular to the bottom surface of the semiconductor chip and lie generally in the same plane,

wherein the second irregular side surface comprises second irregularities that are larger than first irregularities on the first irregular side surface, and

wherein the encapsulating body is in direct contact with the semiconductor chip and directly contacts the first irregular side surface and the second irregular side surface.

2. A semiconductor device according to claim 1 , wherein the second irregular side surface corresponds to two thirds or more of a thickness of the semiconductor chip.

3. A semiconductor device, comprising:

a semiconductor chip having top and bottom surfaces bounded by a side surface;

a die pad on which the bottom surface of the semiconductor chip is disposed;

an adhesive interposed between the bottom surface of the semiconductor chip and the die pad to adhesively bond the semiconductor chip and the die pad;

signal leads extending toward the die pad;

bonding wires connecting respective signal leads to the semiconductor chip; and

an encapsulating resin encapsulating the semiconductor chip, the bonding wires and a part of each signal lead,

wherein the side surface of the semiconductor chip comprises a roughened lower surface portion extending from the bottom surface toward the top surface of the semiconductor chip and on which first roughened surface irregularities are formed, and a roughened upper surface portion extending from the lower surface portion to the top surface of the semiconductor chip and on which second roughened surface irregularities are formed,

wherein the roughened lower and upper surface portions of the side surface lie generally in the same plane,

wherein the second roughened surface irregularities are larger than the first roughened surface irregularities, and

wherein the encapsulating resin is in direct contact with the semiconductor chip and directly contacts the first and second roughened surface irregularities.

4. A semiconductor device according to claim 3 ; wherein the roughened upper surface portion of the side surface extends for two thirds or more of the distance between the top and bottom surfaces of the semiconductor chip.

5. A semiconductor device according to claim 4 ; wherein the roughened lower and upper surface portions of the side surface are generally perpendicular to the bottom surface of the semiconductor chip.

6. A semiconductor device according to claim 3 ; wherein the second roughened surface irregularities are configured to improve the adhesive strength between the roughened upper surface portion and the encapsulating resin as compared to the adhesive strength between the roughened lower surface portion and the encapsulating resin.

7. A semiconductor device according to claim 3 ; wherein the first roughened surface irregularities are configured to allow the adhesive to creep upwardly along the roughened lower surface portion of the side surface during bonding of the semiconductor chip and the die pad to improve adhesive bonding therebetween.

8. A semiconductor device according to claim 7 ; wherein the second roughened surface irregularities are configured to improve the adhesive strength between the roughened upper surface portion and the encapsulating resin as compared to the adhesive strength between the roughened lower surface portion and the encapsulating resin.

9. A semiconductor device according to claim 3 ; wherein the plane is generally perpendicular to the bottom surface of the semiconductor chip.