Memory cell layout for low current field-induced MRAM
Embodiments of the present invention disclose an MRAM cell layout for 32 nm, 45 nm, and 65 nm CMOS process technology.
1. A magnetic random access memory (MRAM) circuit comprising:
a cell;
a bottom electrode located entirely within the cell;
a magnetic tunnel junction (MTJ) structure located in the cell and above the bottom electrode; and
an access transistor including a first terminal, a second terminal, and a gate terminal;
wherein:
the MTJ structure is centered at the center of the cell;
the bottom electrode is not centered at the center of the cell; and
as viewed from directly above the bottom electrode, the first terminal of the access transistor is entirely underneath the bottom electrode.
2. The MRAM circuit of claim 1 , wherein a ratio of a length of the bottom electrode along an axis to a length of the MTJ structure along the same axis is equal to or greater than 1.9.
3. The MRAM circuit of claim 2 , wherein the ratio is 2.1 when the MRAM circuit is fabricated at a 32 nm complementary metal-oxide semiconductor (CMOS) process technology.
4. The MRAM circuit of claim 2 , wherein the ratio is 1.9 when the MRAM circuit is fabricated at a 45 nm CMOS process technology.
5. The MRAM circuit of claim 2 , wherein the ratio is 2.0 when the MRAM circuit is fabricated at a 65 nm CMOS process technology.
6. A magnetic random access memory (MRAM) circuit comprising:
a cell;
a bottom electrode located entirely within the cell;
a magnetic tunnel junction (MTJ) structure located in the cell and above the bottom electrode; and
an access transistor including a first terminal, a second terminal, and a gate terminal;
wherein:
the MTJ structure is centered at the center of the cell and the bottom electrode is not centered at the center of the cell;
as viewed from directly above the bottom electrode, the first terminal of the access transistor is entirely underneath the bottom electrode; and
a ratio of a length of the bottom electrode along an axis to a length of the MTJ structure along the same axis is equal or greater than 1.9.
7. The MRAM circuit of claim 6 , wherein the ratio is 2.1 when the MRAM circuit is fabricated at a 32 nm complementary metal-oxide semiconductor (CMOS) process technology.
8. The MRAM circuit of claim 6 , wherein the ratio is 1.9 when the MRAM circuit is fabricated at a 45 nm CMOS process technology.
9. The MRAM circuit of claim 6 , wherein the ratio is 2.0 when the MRAM circuit is fabricated at a 65 nm CMOS process technology.