IP Library › Granted Patent US 9,093,832
Granted Patent B2
US 9,093,832 · App. 14/619,755 · Granted Jul 28, 2015

Electrical wiring system and method

Inventor: Mark E. Goodson (Corinth, TX)
Assignee: 4G1D HOLDCO LLC
H02G13/80
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Quick Facts
Patent No.
US 9,093,832
App. No.
14/619,755
Granted
Jul 28, 2015
Kind
B2
Abstract

An electrical wiring system/method implementing transient voltage suppression is disclosed. The system/method incorporates HOT, NEUTRAL, GROUND wiring in conjunction with a series drop resistor (SDR) on the HOT conductor that supplies current to the load device. Parallel shunting metal oxide varistors (MOVs) are used in conjunction with corresponding shunt diode rectifiers (SDRs) to suppress transients on the HOT conductor to either the GROUND conductor and/or NEUTRAL conductor. The parallel shunting MOV/SDR pairs may be integrated into a singular structure that is encapsulated in an insulating material to permit implementation of the transient protection wiring system/method into electrical loads and common power distribution equipment such as electrical outlets and power strips.

Claims (144)

1. A surge suppressor system comprising:

(a) metal oxide varistor (MOV);

(b) base metal contact (BMC);

(c) middle metal contact (MMC);

(d) top metal contact (TMC);

(e) semiconductor P-N diode (PND);

(f) first component lead (FCL); and

(g) second component lead (SCL);

wherein

said MOV comprises a first surface and a second surface;

said BMC comprises a first surface and a second surface;

said MMC comprises a first surface and a second surface;

said PND comprises a doped semiconducting material having a first surface and a second surface with a semiconductor P-N junction formed between said PND first surface and said PND second surface;

said TMC comprises a first surface and a second surface;

said FCL is coincident with and electrically contacted to said first surface of said BMC;

said MOV first surface is coincident with and electrically contacted to said BMC second surface;

said MOV second surface is coincident with and electrically contacted to said MMC first surface;

said MMC second surface is coincident with and electrically contacted to said PND first surface;

said PND second surface is coincident with and electrically contacted to said TMC first surface;

said SCL is coincident with and electrically contacted to said second surface of said TMC; and

said FCL contact, said SCL contact, said BMC, said MOV, said MMC, said PND, and said TMC, are encapsulated in an insulating material.

2. The surge suppressor system of claim 1 wherein said PND is oriented such that rectified current flows in said PND from said PND first surface to said PND second surface.

3. The surge suppressor system of claim 1 wherein said PND is oriented such that rectified current flows in said PND from said PND second surface to said PND first surface.

4. The surge suppressor system of claim 1 wherein said PND comprises a Schottky barrier diode.

5. The surge suppressor system of claim 1 wherein said PND comprises a DIAC (diode for alternating current).

6. The surge suppressor system of claim 1 wherein said PND comprises a SIDAC (silicon diode for alternating current).

7. The surge suppressor system of claim 1 wherein said MOV comprises zinc oxide (ZnO) interspersed within a ceramic substrate.

8. The surge suppressor system of claim 1 wherein said BMC, said MOV, said MMC, said PND, and said TMC are cylindrically constructed and concentrically positioned along a common radial axis.

9. A surge suppressor system comprising:

(a) bottom metal oxide varistor (BMV);

(b) top metal oxide varistor (TMV);

(c) base metal contact (BMC);

(d) lower metal contact (LMC);

(e) center metal contact (CMC);

(f) upper metal contact (UMC);

(g) top metal contact (TMC);

(h) first semiconductor P-N diode (FPN);

(i) second semiconductor P-N diode (SPN);

(j) first component lead (FCL);

(k) second component lead (SCL); and

(l) center component lead (CCL);

wherein

said BMV comprises a first surface and a second surface;

said TMV comprises a first surface and a second surface;

said BMC comprises a first surface and a second surface;

said CMC comprises a first surface, a second surface, and a center surface;

said LMC comprises a first surface and a second surface;

said FPN comprises a doped semiconducting material having a first surface and a second surface with a semiconductor P-N junction formed between said FPN first surface and said FPN second surface;

said SPN comprises a doped semiconducting material having a first surface and a second surface with a semiconductor P-N junction formed between said SPN first surface and said SPN second surface;

said UMC comprises a first surface and a second surface;

said TMC comprises a first surface and a second surface;

said FCL is coincident with and electrically contacted to said first surface of said BMC;

said FPN first surface is coincident with and electrically contacted to said BMC second surface;

said FPN second surface is coincident with and electrically contacted to said LMC first surface;

said LMC second surface is coincident with and electrically contacted to said BMV first surface;

said BMV second surface is coincident with and electrically contacted to said CMC first surface;

said CMC second surface is coincident with and electrically contacted to said TMV first surface;

said TMV second surface is coincident with and electrically contacted to said UMC first surface;

said UMC second surface is coincident with and electrically contacted to said SPN first surface;

said SPN second surface is coincident with and electrically contacted to said TMC first surface;

said SCL is coincident with and electrically contacted to said second surface of said TMC;

said CCL is coincident with and electrically contacted to said center surface of said CMC; and

said CCL contact, said FCL contact, said SCL contact, said BMC, said BMV, said LMC, said FPN, said CMC, said SPN, said UMC, said TMV, and said TMC, are encapsulated in an insulating material.

10. The surge suppressor system of claim 9 wherein said FPN is oriented such that rectified current flows in said FPN from said FPN first surface to said FPN second surface and said SPN is oriented such that rectified current flows in said SPN from said SPN first surface to said SPN second surface.

11. The surge suppressor system of claim 9 wherein said FPN and said SPN form a P-N-INTRINSIC-P-N semiconductor structure.

12. The surge suppressor system of claim 9 wherein said FPN and said SPN are Schottky barrier diodes.

13. The surge suppressor system of claim 9 wherein said FPN and said SPN are DIACs (diode for alternating current).

14. The surge suppressor system of claim 9 wherein said FPN and said SPN are SIDACs (silicon diode for alternating current).

15. The surge suppressor system of claim 9 wherein said BMV and said TMV comprise zinc oxide (ZnO) interspersed within a ceramic substrate.

16. The surge suppressor system of claim 9 wherein said BMC, said BMV, said LMC, said FPN, said CMC, said SPN, said UMC, said TMV, and said TMC, are cylindrically constructed and concentrically positioned along a common radial axis.

17. A surge suppressor system comprising:

(a) bottom metal oxide varistor (BMV);

(b) top metal oxide varistor (TMV);

(c) base metal contact (BMC);

(d) lower metal contact (LMC);

(e) center metal contact (CMC);

(f) upper metal contact (UMC);

(g) top metal contact (TMC);

(h) first semiconductor P-N diode (FPN);

(i) second semiconductor P-N diode (SPN);

(j) first component lead (FCL);

(k) second component lead (SCL); and

(l) center component lead (CCL);

wherein

said BMV comprises a first surface and a second surface;

said TMV comprises a first surface and a second surface;

said BMC comprises a first surface and a second surface;

said LMC comprises a first surface and a second surface;

said FPN comprises a doped semiconducting material having a first surface and a second surface with a semiconductor P-N junction formed between said FPN first surface and said FPN second surface;

said CMC comprises a first surface, a second surface, and a center surface;

said SPN comprises a doped semiconducting material having a first surface and a second surface with a semiconductor P-N junction formed between said SPN first surface and said SPN second surface;

said UMC comprises a first surface and a second surface;

said TMC comprises a first surface and a second surface;

said FCL is coincident with and electrically contacted to said first surface of said BMC;

said BMV first surface is coincident with and electrically contacted to said BMC second surface;

said BMV second surface is coincident with and electrically contacted to said LMC first surface;

said LMC second surface is coincident with and electrically contacted to said FPN first surface;

said FPN second surface is coincident with and electrically contacted to said CMC first surface;

said CMC second surface is coincident with and electrically contacted to said SPN first surface;

said SPN second surface is coincident with and electrically contacted to said UMC first surface;

said UMC second surface is coincident with and electrically contacted to said TMV first surface;

said TMV second surface is coincident with and electrically contacted to said TMC first surface;

said SCL is coincident with and electrically contacted to said second surface of said TMC;

said CCL is coincident with and electrically contacted to said center surface of said PND; and

said CCL contact, said FCL contact, said SCL contact, said BMC, said BMV, said LMC, said FPN, said CMC, said SPN, said UMC, said TMV, and said TMC, are encapsulated in an insulating material.

18. The surge suppressor system of claim 17 wherein said FPN is oriented such that rectified current flows in said FPN from said FPN first surface to said FPN second surface and said SPN is oriented such that rectified current flows in said SPN from said SPN first surface to said SPN second surface.

19. The surge suppressor system of claim 17 wherein said FPN and said SPN form a P-N-INTRINSIC-P-N semiconductor structure with said CMC electrically coincident with and contacting the INTRINSIC (I) region of said P-N-INTRINSIC-P-N semiconductor structure.

20. The surge suppressor system of claim 17 wherein said FPN and said SPN are Schottky barrier diodes.

21. The surge suppressor system of claim 17 wherein said FPN and said SPN are DIACs (diode for alternating current).

22. The surge suppressor system of claim 17 wherein said FPN and said SPN are SIDACs (silicon diode for alternating current).

23. The surge suppressor system of claim 17 wherein said BMV and said TMV comprise zinc oxide (ZnO) interspersed within a ceramic substrate.

24. The surge suppressor system of claim 17 wherein said BMC, said BMV, said LMC, said FPN, said CMC, said SPN, said UMC, said TMV, and said TMC, are cylindrically constructed and concentrically positioned along a common radial axis.

25. A surge suppressor system comprising:

(a) bottom metal oxide varistor (BMV);

(b) top metal oxide varistor (TMV);

(c) base metal contact (BMC);

(d) lower metal contact (LMC);

(e) center metal contact (CMC);

(f) upper metal contact (UMC);

(g) top metal contact (TMC);

(h) P-N-I-P-N semiconductor diode (PND);

(i) first component lead (FCL);

(j) second component lead (SCL); and

(k) center component lead (CCL);

wherein

said BMV comprises a first surface and a second surface;

said TMV comprises a first surface and a second surface;

said BMC comprises a first surface and a second surface;

said LMC comprises a first surface and a second surface;

said PND comprises a doped semiconducting material having a first surface, a second surface, and a center surface with a semiconductor P-N-INTRINSIC-P-N layered junction formed between said PND first surface and said PNL second surface and said center surface electrically contacting said INTRINSIC region of said semiconductor P-N-INTRINSIC-P-N layered junction;

said UMC comprises a first surface and a second surface;

said TMC comprises a first surface and a second surface;

said FCL is coincident with and electrically contacted to said first surface of said BMC;

said BMV first surface is coincident with and electrically contacted to said BMC second surface;

said BMV second surface is coincident with and electrically contacted to said LMC first surface;

said LMC second surface is coincident with and electrically contacted to said PND first surface;

said PND second surface is coincident with and electrically contacted to said UMC first surface;

said UMC second surface is coincident with and electrically contacted to said TMV first surface;

said TMV second surface is coincident with and electrically contacted to said TMC first surface;

said SCL is coincident with and electrically contacted to said second surface of said TMC;

said CCL is coincident with and electrically contacted to said center surface of said PND; and

said CCL contact, said FCL contact, said SCL contact, said BMC, said BMV, said LMC, said PND, said UMC, said TMV, and said TMC, are encapsulated in an insulating material.

26. The surge suppressor system of claim 25 wherein said BMV and said TMV comprise zinc oxide (ZnO) interspersed within a ceramic substrate.

27. The surge suppressor system of claim 25 wherein said BMC, said BMV, said LMC, said PND, said UMC, said TMV, and said TMC, are cylindrically constructed and concentrically positioned along a common radial axis.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 8, 2019
From: GOODSON, MARK
To: 4G1D HOLDCO, LLC
Reel/Frame 050955/0593 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 22, 2015
From: GOODSON, MARK E.
To: 4G1D HOLDCO LLC
Reel/Frame 035878/0553 →
Continuity (2)
Continuation In Part 13455686 · Apr 25, 2012
Related Publication 20150155695A1 · Jun 4, 2015