Semiconductor device including retention circuit
View Patent ↗A semiconductor device includes first power lines through which first power is supplied, a plurality of unit regions defined by the first power lines, and second power lines through which second power is supplied. Each of the unit regions includes a logic circuit suitable for operating by receiving the first power from at least one of the first power lines during a normal mode, and a retention circuit suitable for operating by receiving the second power from at least one of the second power lines, receiving data from the logic circuit when an operation mode changes from the normal mode to a sleep mode, and keeping the data during the sleep mode. The logic circuit is electrically separated from the second power lines.
1. A semiconductor device comprising:
first power lines through which first power is supplied;
a plurality of unit regions defined by the first power lines; and
second power lines through which second power is supplied,
wherein each of the unit regions comprises:
a logic circuit suitable for operating by receiving the first power from at least one of the first power lines during a normal mode; and
a retention circuit suitable for operating by receiving the second power from at least one of the second power lines, receiving data from the logic circuit when an operation mode changes from the normal mode to a sleep mode, and keeping the data during the sleep mode,
wherein the logic circuit is electrically separated from the second power lines.
2. The semiconductor device of claim 1 , wherein the unit regions are defined in a grid by the first power lines.
3. The semiconductor device of claim 1 , wherein the first power is blocked and the second power is supplied to the unit regions, during the sleep mode.
4. The semiconductor device of claim 1 , wherein the second power is supplied to the retention circuit during the normal mode and the sleep mode.
5. The semiconductor device of claim 1 , wherein, in a corresponding unit region, the retention circuit is provided in an area separated from an area in which the logic circuit is provided.
6. The semiconductor device of claim 1 , wherein the retention circuit includes a storage unit suitable for storing the data during the sleep mode.
7. The semiconductor device of claim 1 , wherein the retention circuit includes a plurality of retention flip-flops suitable for storing the data during the sleep mode.
8. The semiconductor device of claim 1 , wherein the logic circuit includes a plurality of logics and normal flip-flops using the first power,
the retention circuit includes a plurality of retention flip-flops using the second power, and
the retention flip-flops receive the data latched in the normal flip-flops when an operation mode changes from the normal mode to the sleep mode and keep the data.
9. The semiconductor device of claim 8 , wherein the normal flip-flops and the retention flip-flops form a scan chain.
10. The semiconductor device of claim 1 , further comprising a clock generation block suitable for generating first and second clocks.
11. The semiconductor device of claim 10 , wherein the logic circuit included in a first unit region among the unit regions includes first logics and first normal flip-flops suitable for operating in synchronization with the first clock.
12. The semiconductor device of claim 11 , wherein the retention circuit included in the first unit region includes first retention flip-flops suitable for receiving data from the first normal flip-flops in synchronization with the first clock when an operation mode changes from the normal mode to the sleep mode and keeping the data received from the first normal flip-flops.
13. The semiconductor device of claim 12 , wherein the first normal flip-flops and the first retention flip-flops form a scan chain.
14. The semiconductor device of claim 12 , wherein the first unit region comprises a first demultiplexer suitable for receiving the data from the logic circuit in the first unit region, transmitting the received data to a second logic circuit included in a second unit region among the unit regions during the normal mode, and transmitting the received data to the first retention circuit during the sleep mode.
15. The semiconductor device of claim 10 , wherein the logic circuit included in a second unit region among the unit regions comprises:
second logics and second normal flip-flops suitable for operating in synchronization with the first clock; and
third logics and third normal flip-flops suitable for operating in synchronization with the second clock.
16. The semiconductor device of claim 15 , wherein a retention circuit in the second unit region comprises:
second retention flip-flops suitable for receiving data from the second normal flip-flops in synchronization with the first clock when an operation mode changes from the normal mode to the sleep mode and keeping the data received from the second normal flip-flops; and
third retention flip-flops suitable for receiving data from the third normal flip-flops in synchronization with the second clock when an operation mode changes from the normal mode to the sleep mode and keeping the data received from the third normal flip-flops.
17. The semiconductor device of claim 16 , wherein the second normal flip-flops and the second retention flip-flops form a first scan chain, and
the third normal flip-flops and the third retention flip-flops form a second scan chain.