ISOLATION METHODS FOR LEAKAGE, LOSS AND NON-LINEARITY MITIGATION IN RADIO-FREQUENCY INTEGRATED CIRCUITS ON HIGH-RESISTIVITY SILICON-ON-INSULATOR SUBSTRATES

1 . A radio frequency integrated circuit comprising:

a silicon-on-insulator substrate including a buried oxide layer disposed over a silicon substrate and a silicon layer disposed over the buried oxide layer;

at least one transistor disposed on the silicon layer, each transistor including a gate, a drain, a source, and a body; and

a guard-ring on the silicon-on-insulator substrate surrounding the at least one transistor on the silicon layer;

wherein depletion regions on the silicon substrate corresponding to areas surrounding the at least one transistor are defined by the application of a voltage to the guard-ring.

2 . The radio frequency integrated circuit of claim 1 , wherein the silicon substrate is a high-resistivity silicon substrate.

3 . The radio frequency integrated circuit of claim 1 , further comprising a gate oxide layer disposed between the guard-ring and the silicon-on-insulator substrate.

4 . The radio frequency integrated circuit of claim 1 , wherein the guard-ring is a high-resistivity conductive material.

5 . The radio frequency integrated circuit of claim 4 , wherein the guard-ring is constructed of polysilicon.

6 . The radio frequency integrated circuit of claim 1 , wherein the body of the at least one transistor is connected to the source thereof.

7 . The radio frequency integrated circuit of Claiml, wherein the body of the at least one transistor is independent of the source thereof.

8 . The radio frequency integrated circuit of claim 1 , wherein the body of the at least one transistor is connected to the drain thereof.

9 . The radio frequency integrated circuit of claim 1 , wherein the body of the at least one transistor is independent of the drain thereof.

10 . The radio frequency integrated circuit of claim 1 , wherein the at least one transistor includes first and second n-channel metal oxide semiconductor field effect transistors.

11 . The radio frequency integrated circuit of claim 1 , wherein the at least one transistor includes a first n-channel metal oxide semiconductor field effect transistor and a second p-channel metal oxide semiconductor field effect transistor.

12 . The radio frequency integrated circuit of claim 5 , wherein the guard-ring limits a parasitic surface conduction (PSC) layer to one or more portions of the silicon substrate underlying the first and second NMOS transistors.

13 . A radio frequency integrated circuit, comprising:

a semiconductor substrate;

a buried oxide layer over the semiconductor substrate;

a first dielectric layer over the buried oxide layer;

at least one radio frequency transmission line over the first dielectric layer; and

at least one polysilicon line disposed on each of the opposite sides of the radio frequency transmission line in a spaced relationship;

wherein depletion regions on the semiconductor substrate corresponding to areas overlapping the at least one polysilicon line are defined by the application of a voltage to the at least one polysilicon line.

14 . The radio frequency integrated circuit of claim 13 , wherein the at least one polysilicon line limits a parasitic surface conduction layer to one or more portions of the semiconductor substrate underlying the at least one radio frequency transmission line.

15 . A radio frequency integrated circuit, comprising:

a semiconductor substrate;

a buried oxide layer over the semiconductor substrate;

a plurality of dielectric layers over the buried oxide layer;

at least one radio frequency transmission line over the plurality of dielectric layers; and

a plurality of isolation traces in a lateral spaced relationship to the at least one radio frequency transmission line, each of the plurality of isolation traces being longitudinally offset on a corresponding one of the plurality of dielectric layers;

wherein depletion regions on the semiconductor substrate corresponding to areas overlapping the plurality of isolation traces are defined by the application of a voltage to the plurality of isolation traces.

16 . The radio frequency integrated circuit of claim 15 , wherein the plurality of isolation traces are metal layers.

17 . The radio frequency integrated circuit of claim 15 , wherein the plurality of isolation traces are polysilicon layers.

18 . The radio frequency integrated circuit of claim 15 , wherein a one of the plurality of isolation traces is placed within a shallow trench isolation (STI) trench defined by a first one of the plurality of dielectric layers.

19 . The radio frequency integrated circuit of claim 18 , wherein a second one of the plurality of isolation traces is placed on a second one of the plurality of dielectric layers.

20 . The radio frequency integrated circuit of claim 18 , wherein the isolation traces are disposed on each of the opposite sides of the at least one radio frequency transmission line and are electrically connected together.

21 . The radio frequency integrated circuit of claim 20 , wherein a distance between each of the plurality of isolation traces is lower than a wavelength of a signal on the radio frequency transmission line.

22 . A radio frequency integrated circuit, comprising:

a semiconductor substrate;

a buried oxide layer over the semiconductor substrate;

one or more dielectric layers, a first one of the one or more dielectric layers being disposed over the buried oxide layer;

a coplanar wave guide structure over the first one of the one or more dielectric layers, the coplanar wave guide structure including a ground plane and a central conductor; and

a plurality of first isolation traces in a spaced, parallel relationship to the central conductor, the first isolation traces being disposed within lateral gaps defined by the ground plane and the central conductor;

wherein depletion regions on the semiconductor substrate corresponding to areas overlapping with the plurality of first isolation traces are defined by the application of a voltage to the first isolation traces.

23 . The radio frequency integrated circuit of claim 22 , wherein the plurality of first isolation traces is disposed on the first one of the one or more dielectric layers.

24 . The radio frequency integrated circuit of claim 22 , wherein the plurality of first isolation traces is disposed on a second one of the one or more dielectric layers, the second one of the one or more dielectric layers being disposed over the coplanar wave guide structure.

25 . The radio frequency integrated circuit of claim 22 , wherein the plurality of first isolation traces are polysilicon layers.

26 . The radio frequency integrated circuit of claim 22 , wherein at least one of the plurality of first isolation traces is disposed under the ground plane.

27 . The radio frequency integrated circuit of claim 22 , further comprising:

a plurality of second isolation traces in a spaced, parallel relationship to each other and orthogonal to the plurality of first isolation traces;

wherein the depletion regions further corresponding to areas overlapping with the plurality of second isolation traces are defined by the application of a voltage to the second isolation traces.