Modulator and modulation method using non-uniform 16-symbol signal constellation for low-density parity check codeword having 4/15 code rate

1. A modulator using a non-uniform 16-symbol signal constellation, comprising:

a memory configured to receive a codeword corresponding to a low-density parity check (LDPC) code having a code rate of 4/15; and

a processor configured to map the codeword to 16 symbols of the non-uniform 16-symbol signal constellation on a 4-bit basis, thereby generating a modulated signal,

wherein the 16 symbols are defined as shown in the following Table:

TABLE

W

Constellation

0

 0.3412 + 0.5241i

1

 0.5241 + 0.3412i

2

 0.5797 + 1.1282i

3

 1.1282 + 0.5797i

4

−0.3412 + 0.5241i

5

−0.5241 + 0.3412i

6

−0.5797 + 1.1282i

7

−1.1282 + 0.5797i

8

 0.3412 − 0.5241i

9

 0.5241 − 0.3412i

10

 0.5797 − 1.1282i

11

 1.1282 − 0.5797i

12

−0.3412 − 0.5241i

13

−0.5241 − 0.3412i

14

−0.5797 − 1.1282i

15

−1.1282 − 0.5797i,

and

wherein the modulated signal corresponds to a transmission signal, the transmission signal being transmitted to a reception device.

2. The modulator of claim 1 , wherein the LDPC code is interleaved on a bit group basis before mapping the codeword to the non-uniform 16-symbol signal constellation.

3. The modulator of claim 2 , wherein the LDPC code is interleaved using the following equation using permutation order:

Y j =X π(j) 0≦ j≦N group

where X π(j) is a π(j)th bit group, Y j is an interleaved j-th bit group, N group is a number of bit groups, and π(j) is a permutation order for bit group-based interleaving.

4. The modulator of claim 1 , wherein the LDPC code is generated by performing accumulation at parity bit addresses of a memory, the parity bit addresses updated using a sequence corresponding to a parity check matrix (PCM).