IP Library Granted Patent US 9,361,158
Granted Patent B2
US 9,361,158 · App. 14/621,777 · Granted Jun 7, 2016

Wireless bus for intra-chip and inter-chip communication, including embodiments with adaptable links

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Quick Facts
Patent No.
US 9,361,158
App. No.
14/621,777
Granted
Jun 7, 2016
Kind
B2
Abstract

Embodiments of the present invention are directed to a scalable wireless bus for intra-chip and inter-chip communication. The scalable wireless bus includes a plurality of wireless-enabled components (WECs). In an embodiment, the scalable wireless bus may have at least one of the number of links among WECs and the capacity of said links adapted based on one or more factors. For example, the number of links and the capacity of the links may be adapted according to one or more of, among other factors, expected activity level over the wireless bus, desired power consumption, delay, and interference levels.

Claims (36)

1. A wireless bus system, comprising:

a plurality of wireless-enabled components (WECs) coupled via a plurality of wireless links; and

a controller, coupled to at least one of the plurality of WECs via at least one control link, the controller configured to identify proximally located WECs, configure communications among the plurality of WECs, and adapt the plurality of wireless links;

wherein the controller is further configured to obtain a power consumption level of the wireless bus system and adapt the plurality of wireless links according to the power consumption level of the wireless bus system; and

wherein the controller is further configured to adapt the plurality of wireless links for the plurality of WECs to utilize a higher number of the plurality of wireless links during a high power consumption level and a lower number of the plurality of wireless links during a low power consumption level.

2. The wireless bus system of claim 1 , wherein a first WEC of the plurality of WECs is associated with a first integrated circuit and wherein a second WEC of the plurality of WECs is associated with a second integrated circuit, and wherein the first integrated circuit and the second integrated circuit are located in different devices.

3. The wireless bus system of claim 1 , wherein at least one WEC of the plurality of WECs is configured to increase and decrease a capacity of at least one wireless link of the plurality of wireless links; and

wherein the controller is further configured to adapt the capacity of the at least one wireless link according to the power consumption level of the wireless bus system.

4. The wireless bus system of claim 3 , wherein the at least one WEC configured to increase and decrease the capacity of the at least one wireless link increases or decreases the capacity using at least one of the following: transmit power, modulation scheme, or error coding.

5. The wireless bus system of claim 1 , wherein the controller is further configured to adapt the plurality of wireless links according to an interference level threshold, wherein the interference level threshold is set according to a desired signal quality.

6. The wireless bus system of claim 1 , wherein the controller is further configured to adapt the plurality of wireless links according to an expected power consumption level.

7. The wireless bus system of claim 1 , wherein at least one WEC of the plurality of WECs is configured to increase or decrease a wireless link of the plurality of wireless links using polarization diversity.

8. A wireless bus system, comprising:

a plurality of wireless-enabled components (WECs) coupled via a plurality of wireless links; and

a controller, coupled to at least one of the plurality of WECs via at least one control link, the controller configured to identify proximally located WECs, configure communications among the plurality of WECs, and adapt the plurality of wireless links;

wherein the controller is further configured to obtain a power consumption level of the wireless bus system, obtain a desired power consumption level, and adapt the plurality of wireless links according to the desired power consumption level of the wireless bus system; and

wherein the controller is further configured to adapt the plurality of wireless links to shorter range wireless links for lower power consumption and longer range wireless links for higher power consumption.

9. The wireless bus system of claim 8 , wherein a first WEC of the plurality of WECs is associated with a first integrated circuit and wherein a second WEC of the plurality of WECs is associated with a second integrated circuit, and wherein the first integrated circuit and the second integrated circuit are located in different devices.

10. The wireless bus system of claim 8 , wherein at least one WEC of the plurality of WECs is configured to increase and decrease a capacity of at least one wireless link of the plurality of wireless links;

wherein the controller is further configured to adapt the capacity of the at least one wireless link according to the desired power consumption level of the wireless bus system; and

wherein increasing the capacity of tie at least one wireless link increases the power consumption level and decreasing the capacity of the at least one wireless link decreases the power consumption level.

11. The wireless bus system of claim 10 , wherein the at least one WEC configured to increase and decrease the capacity of the at least one wireless link increases or decreases the capacity using at least one of the following: transmit power, modulation scheme, or error coding.

12. The wireless bus system of claim 8 , wherein the controller is further configured to adapt the plurality of wireless links to a configuration that uses a higher power consumption level if the higher power consumption level can be accommodated.

13. The wireless bus system of claim 8 , wherein the controller is further configured to adapt the plurality of wireless links to have longer range wireless links and more direct wireless links when the higher power consumption level can be accommodated or a lower delay is desired.

14. The wireless bus system of claim 8 , wherein at least one WEC of the plurality of WECs is configured to increase or decrease a capacity of a wireless link of the plurality of wireless links using polarization diversity.

15. A method of scaling a wireless bus comprising:

wirelessly coupling a plurality of wireless-enabled components (WECs) via a plurality of wireless links, wherein the plurality of wireless links form the wireless bus;

sending a communication signal from a first WEC of the plurality of WECs to a second WEC of the plurality of WECs;

selecting a threshold level, wherein the threshold level is at least one of: a desired power consumption, an acceptable communication delay, or an acceptable signal quality;

detecting a change in power consumption over the wireless bus; and

adapting the plurality of wireless links to increase or decrease in number when the detected power consumption over the wireless bus is higher than the selected threshold.

16. The method of claim 15 , wherein the first WEC of the plurality of WECs is associated with a first integrated circuit and wherein the second WEC of the plurality of WECs is associated with a second integrated circuit, and wherein the first integrated circuit and the second integrated circuit are located in different devices.

17. The method of claim 15 , further comprising increasing or decreasing the capacity of the plurality of wireless links by varying at least one of: a transmit power, a modulation scheme, or an error coding scheme associated with at least one of the plurality of wireless links.

18. The method of claim 15 , further comprising transmitting a wireless signal to scan a surrounding area for proximally located WECs.

19. The method of claim 15 , further comprising sending requests via a controller over a control channel, wherein the controller is a WEC.

20. The method of claim 15 , wherein adapting the plurality of wireless links to increase or decrease in number is accomplished using polarization diversity.

Assignments (6)
CORRECTIVE ASSIGNMENT TO CORRECT THE PATENT NUMBER 9,385,856 TO 9,385,756 PREVIOUSLY RECORDED AT REEL: 47349 FRAME: 001. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Mar 22, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 051144/0648 →
CORRECTIVE ASSIGNMENT TO CORRECT THE EFFECTIVE DATE PREVIOUSLY RECORDED ON REEL 047229 FRAME 0408. ASSIGNOR(S) HEREBY CONFIRMS THE THE EFFECTIVE DATE IS 09/05/2018. Recorded Oct 29, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047349/0001 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047229/0408 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: BROADCOM CORPORATION
Reel/Frame 041712/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 1, 2017
From: BROADCOM CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041706/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: BROADCOM CORPORATION
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037806/0001 →