Granted Patent B1

US 9,779,197 · App. 14/622,254 · Granted Oct 3, 2017

Abstract

Claims (41)

1. A method of merging one-bit cells in an integrated circuit layout, the method comprising:

identifying, using a computer processor, a set of merge candidate one-bit cells in the integrated circuit layout based on at least an instance naming pattern of the one-bit cells such that each of the one-bit cells in the merge candidate set has at least a part of its cell name in common with all other cells in the merge candidate set, the integrated circuit layout stored in a database;

determining, using the processor, a set of merge cells, from among the cells in the merge candidate set, to be merged into a multi-bit register, the determination of the set of merge cells being based on each merge cell being located within a merge distance from each of the other merge cells in the set of merge cells, and each merge cell sharing a clock with the other merge cells in the set of merge cells; and

generating, using the processor, instructions to a placer for merging the set of merge cells to form the multi-bit register in the integrated circuit layout.

2. The method of claim 1 , wherein determining the set of merge cells is further based on each merge cell having the same track height as each of the other merge cells in the set of merge cells.

3. The method of claim 1 , wherein determining the set of merge cells is further based on each merge cell having the same channel length as each of the other merge cells in the set of merge cells.

4. The method of claim 1 , wherein determining the set of merge cells is further based on each merge cell having the same threshold voltage as each of the other merge cells in the set of merge cells.

5. The method of claim 1 , wherein determining the set of merge cells is further based on each merge cell sharing a common enable with each of the other merge cells in the set of merge cells.

6. The method of claim 1 , wherein determining the set of merge cells is further based on each merge cell having the same reset or set type as each of the other merge cells in the set of merge cells.

7. The method of claim 6 , wherein determining the set of merge cells is further based on each merge cell sharing a common reset or set with each of the other merge cells in the set of merge cells.

8. The method of claim 1 , wherein determining the set of merge cells is further based on each merge cell having the same scan-in type as each of the other merge cells in the set of merge cells.

9. The method of claim 8 , wherein determining the set of merge cells is further based on each merge cell sharing a common scan-in enable with each of the other merge cells in the set of merge cells.

10. The method of claim 1 , wherein determining the set of merge cells is further based on each merge cell being located within a merge area of 100 μm by 100 μm of the other merge cells in the set of merge cells.

11. The method of claim 10 , wherein the merge area is defined by a sliding window that is moved incrementally across the integrated circuit layout in both horizontal and vertical directions.

12. The method of claim 1 , wherein the set of merge candidate one-bit cells is a first set of merge candidate one-bit cells and wherein the set of merge cells is a first set of merge cells, the method further comprising:

identifying a second set of merge candidate one-bit cells in the integrated circuit layout;

determining a second set of merge cells, from among cells in the second merge candidate set, to be merged into a second multi-bit register, the determination of the second set of merge cells being based on each merge cell being located within a merge distance from each of the other merge cells in the second set of merge cells, and each merge cell sharing a clock with the other merge cells in the second set of merge cells; and

generating instructions to the placer for merging the second set of merge cells to form the second multi-bit register in the integrated circuit layout.

13. The method of claim 1 , further comprising:

determining functional timing constraints for the merge candidate set of one-bit cells based on timing constraints data; and

excluding the one-bit cells having functional timing constraints from the set of merge cells.

14. The method of claim 1 , further comprising optimizing the placement of the multi-bit register in the integrated circuit layout.

15. The method of claim 1 , further comprising optimizing the placement of the merge candidate set of one-bit cells in the integrated circuit layout before determining the set of merge cells.

16. A system for merging one-bit cells in an integrated circuit layout, comprising:

a database to store the integrated circuit layout;

a placer in communication with the database to update the integrated circuit layout; and

a merger in communication with the placer and configured to:

identify a set of merge candidate one-bit cells in the integrated circuit layout based on at least an instance naming pattern of the one-bit cells such that each of the one-bit cells in the merge candidate set has at least a part of its cell name in common with all other cells in the merge candidate set;

determine a set of merge cells, from among the cells in the merge candidate set, to be merged into a multi-bit register, the determination of the set of merge cells being based on each merge cell being located within a merge distance from each of the other merge cells in the set of merge cells, and each merge cell sharing a clock with the other merge cells in the set of merge cells; and

generate instructions to a placer for merging the set of merge cells to form the multi-bit register in the integrated circuit layout.

17. The system of claim 16 , wherein the merger comprises a sliding window having a merge area of 100 μm by 100 μm to define the merge distance, wherein the sliding window is moved incrementally across the integrated circuit layout in both horizontal and vertical directions.

18. The system of claim 16 , wherein the merger is further configured to:

determine functional timing constraints for the merge candidate set of one-bit cells based on timing constraints data; and

exclude the one-bit cells having functional timing constraints from the set of merge cells.

19. A method of using a system for merging one-bit cells in an integrated circuit layout, the method comprising:

building the integrated circuit layout in a database based on inputs comprising: a logical netlist, constraints, and a floorplan;

operating a placer to place the one-bit cells and route connections between the one-bit cells in the integrated circuit layout;

identifying, using a computer processor, with a merger, a set of merge candidate one-bit cells in the integrated circuit layout based on at least an instance naming pattern of the one-bit cells such that each of the one-bit cells in the merge candidate set has at least a part of its cell name in common with all other cells in the merge candidate set;

determining, using the computer processor, with the merger, a set of merge cells, from among the cells in the merge candidate set, to be merged into a multi-bit register, the determination of the set of merge cells being based on each merge cell being located within a merge distance from each of the other merge cells in the set of merge cells, and each merge cell sharing a clock with the other merge cells in the set of merge cells;

generating, using the computer processor, by the merger, instructions to a placer for merging the set of merge cells to form the multi-bit register in the integrated circuit layout; and

further operating the placer to re-route the connections between the set of merge cells in order to the update the integrated circuit layout.

Assignments (9)