Intelligent chassis management
View Patent ↗A modular system uses point-to-point communication between field-programmable gate arrays (FPGAs) on a control module and each port module, respectively, to manage basic module functions, such as power, environmental monitoring, and health checks on the modules and their components. This allows a chassis to be managed without fully powering each card first, frees processors on the modules from having to perform health checks, allows dedicated resources to rapidly monitor the health of each card, and prevents one bad card from disabling management of all cards.
1. A networking device, comprising:
a line module that includes:
a plurality of external network ports that are configured to send and receive data packets through a network;
a line processor that is coupled to the plurality of external network ports; and
a line dedicated hardware resource that is coupled to the line processor, wherein the line dedicated hardware resource is configured to receive power when the line processor is powered down and monitor a plurality of components that are included in the line module without involvement of the line processor;
a route module that is configured to perform route processing of data packets received by the line module through the network, wherein the route module includes:
a route processor; and
a route dedicated hardware resource that is coupled to the route processor, wherein the route dedicated hardware resource is configured to receive power when the route processor is powered down; and
a point-to-point connection between the route dedicated hardware resource and the line dedicated hardware resource, wherein the route dedicated hardware resource is configured to transmit, over the point-to-point connection to the line dedicated hardware resource, a clock signal that is used by the route dedicated hardware resource and the line dedicated hardware resource to transmit control plane data over the point-to-point connection while at least one of the route processor and the line processor are powered down.
2. The networking device of claim 1 , wherein the point-to-point connection includes a first unidirectional signal path that is configured to transmit the clock signal, a second unidirectional signal path that is configured to transmit the control plane data from the route dedicated hardware resource to the line dedicated hardware resource, and a third unidirectional signal path that is configured to transmit the control plane data from the line dedicated hardware resource to the route dedicated hardware resource.
3. The networking device of claim 1 , wherein the line dedicated hardware resource is configured to transmit, over the point-to-point connection to the route dedicated hardware resource, the control plane data that includes a data frame with an operation code that is indicative of one of:
a startup of the line dedicated hardware resource subsequent to a power up or reset of the line dedicated hardware resource such that the line dedicated hardware resource is ready to communicate; and
a shutdown of the line module such that the line processor is not receiving power while the line dedicated hardware resource is receiving power.
4. The networking device of claim 1 , wherein the line dedicated hardware resource is configured to transmit, over the point-to-point connection to the route dedicated hardware resource, the control plane data that includes a first data frame with an operation code that is indicative of a request to read data from an address of a register in the route module.
5. The networking device of claim 4 , wherein the route dedicated hardware resource is configured to send, over the point-to-point connection to the line dedicated hardware resource, the control plane data that includes a second data frame with an operation code that is indicative of a value that was read from the address of the register in the route module, along with the value that was read.
6. The networking device of claim 1 , wherein the line dedicated hardware resource is configured to transmit, over the point-to-point connection to the route dedicated hardware resource, the control plane data that includes a first data frame with an operation code that is indicative of a request to write data to an address of a register in the route module, along with a value to be written.
7. The networking device of claim 6 , wherein the route dedicated hardware resource is configured to transmit, over the point-to-point connection to the line dedicated hardware resource, the control plane data that includes a second data frame with an operation code that is indicative of a success or a failure in writing the value to the address of the register in the route module.
8. A networking device, comprising:
a plurality of line cards that each include:
a plurality of external network ports that are configured to send and receive data packets through a network;
a line processor that is coupled to the plurality of external network ports; and
a line Field Programmable Gate Array (FPGA) that is coupled to the line processor, wherein the line FPGA is configured to receive power when the line processor is powered down and monitor a plurality of components that are included in its line card without involvement of the line processor;
a route processor manager (RPM) card that is configured to perform route processing of the data packets received by the plurality of line cards through the network, wherein the RPM card includes:
a route processor; and
a route FPGA that is coupled to the route processor, wherein the route FPGA is configured to receive power when the route processor is powered down; and
a dedicated serial bus connection between the route FPGA and each respective line FPGA, wherein the route FPGA is configured to transmit, over each of the dedicated serial bus connections to each respective line FPGA, a clock signal that is used by the route FPGA and each respective line FPGA to transmit control plane data over the dedicated serial bus connection while at least one of the route processor and the line processor are powered down.
9. The networking device of claim 8 , wherein each dedicated serial bus connection includes a first unidirectional signal path that is configured to transmit the clock signal, a second unidirectional signal path that is configured to transmit the control plane data from the route FPGA to the line FPGA connected to that dedicated serial bus connection, and a third unidirectional signal path that is configured to transmit the control plane data from the line FPGA connected to that dedicated serial bus connection to the route FPGA.
10. The networking device of claim 8 , wherein each line FPGA is configured to transmit, over its dedicated serial bus connection to the route FPGA, the control plane data that includes a data frame with an operation code that is indicative of one of:
a startup of that line FPGA subsequent to a power up or reset of that line FPGA such that that line FPGA is ready to communicate; and
a shutdown of the line card that includes that line FPGA such that the line processor on that line card is not receiving power while that line FPGA is receiving power.
11. The networking device of claim 8 , wherein each line FPGA is configured to transmit, over its dedicated serial bus connection to the route FPGA, the control plane data that includes a first data frame with an operation code that is indicative of a request to read data from an address of a register in the RPM card.
12. The networking device of claim 11 , wherein the route FPGA is configured to transmit, over each dedicated serial bus connection to each respective line FPGA, the control plane data that includes a second data frame with an operation code that is indicative of a value that was read from the address of the register in the RPM card, along with the value that was read.
13. The networking device of claim 8 , wherein each line FPGA is configured to, over its dedicated serial bus connection to the route FPGA, the control plane data that includes a first data frame with an operation code that is indicative of a request to write data to an address of a register in the RPM card, along with a value to be written.
14. The networking device of claim 13 , wherein the route FPGA is configured to transmit, over each dedicated serial bus connection to each respective line FPGA, the control plane data that includes a second data frame with an operation code that is indicative of a success or a failure in writing the value to the address of the register in the RPM card.
15. A method for managing a networking device, comprising:
powering a line dedicated hardware resource in a line module while a line processor in the line module is powered down, wherein the line module includes a plurality of external network ports that are coupled to the line processor and that are configured to send and receive data packets through a network;
powering a route dedicated hardware resource in a route module while a route processor in the route module is powered down, wherein the route module is configured to perform route processing of data packets received by the line module through the network
monitoring, using the line dedicated hardware resource, a plurality of components that are included in the line module without involvement of the line processor;
transmitting, by the route dedicated hardware resource, a clock signal over a point-to-point connection between the line dedicated hardware resource and the route dedicated hardware resource; and
transmitting, by each of the route dedicated hardware resource and the line dedicated hardware resource, control plane data over the point-to-point connection using the clock signal.
16. The method of claim 15 , further comprising:
transmitting the clock signal from the route dedicated hardware resource to the line dedicated hardware resource over a first unidirectional signal path that is included in the point-to-point connection;
transmitting the control plane data from the route dedicated hardware resource to the line dedicated hardware resource over a second unidirectional signal path that is included in the point-to-point connection; and
transmitting the control plane data from the line dedicated hardware resource to the route dedicated hardware resource over a third unidirectional signal path that is included in the point-to-point connection.
17. The method of claim 15 , further comprising:
transmitting, by the line dedicated hardware resource over the point-to-point connection to the route dedicated hardware resource, the control plane data that includes a data frame with an operation code that is indicative of one of:
a startup of the line dedicated hardware resource subsequent to a power up or reset of the line dedicated hardware resource such that the line dedicated hardware resource is ready to communicate; and
a shutdown of the line module such that the line processor is not receiving power while the line dedicated hardware resource is receiving power.
18. The method of claim 15 , further comprising:
transmitting, by the line dedicated hardware resource over the point-to-point connection to the route dedicated hardware resource, the control plane data that includes a first data frame with an operation code that is indicative of a request to read data from an address of a register in the route module.
19. The method of claim 18 , further comprising:
transmitting, by the route dedicated hardware resource over the point-to-point connection to the line dedicated hardware resource, the control plane data that includes a first data frame with an operation code that is indicative of a value that was read from the address of the register in the route module, along with the value that was read.
20. The method of claim 15 , further comprising:
transmitting, by the line dedicated hardware resource over the point-to-point connection to the route dedicated hardware resource, the control plane data that includes a first data frame with an operation code that is of a request to write data to an address of a register in the route module, along with a value to be written; and
transmitting, by the route dedicated hardware resource over the point-to-point connection to the line dedicated hardware resource, the control plane data that includes a second data frame with an operation code that is indicative of a success or a failure in writing the value to the address of the register in the route module.