N-valued shift registers with inverter reduced feedback logic functions
Shift register based circuits include non-binary polynomial calculation circuits, coder circuits, scramblers, descramblers and sequence generators that apply non-binary two-input/single output switching functions wherein at least one input contains a non-binary inverter or multiplier. A combination of a two-input/single output non-binary switching device with at least one non-binary inverter at an input is advantageously reduced to a single device that implements a single non-binary switching function. The reduced single device may be an electronic memory that stores the truth table of the single non-binary switching function.
1. A device to generate n-valued symbols, each n-valued symbol having one of n values with n=2 p and p>1 and being represented by a signal, comprising:
an n-valued shift register with feedback, including a plurality of shift register elements and a memory implementing an n-valued logic feedback function;
the memory having a first input and a second input, the memory storing a single non-commutative n-valued truth table implementing the n-valued logic feedback function, which is an addition over an n-valued finite field that is modified by an n-valued inverter, the memory being connected to the n-valued shift register with feedback, wherein the first input and the second input each are enabled to receive an n-valued symbol provided by a shift register element of the n-valued shift register that determine a symbol in the single non-commutative n-valued truth table as an output symbol of the n-valued logic feedback function;
an output of the shift register with feedback to provide an n-valued symbol, wherein the device is selected from the group consisting of: scrambler, descrambler, sequence generator, generator of symbols of an error correction code, and a Cyclic Redundancy Check (CRC) coder.
2. The device of claim 1 , wherein the error correction code is at least one of a Reed Solomon code or a convolutional code.
3. The device of claim 1 , wherein the n-valued inverter is a multiplier over the n-valued finite field.
4. The device of claim 1 , wherein the n-valued inverter is not a multiplier over the n-valued finite field.
5. The device of claim 1 , wherein an n-valued symbol is represented by a plurality of binary symbols.
6. The device of claim 1 , wherein the shift register with feedback is a Linear Feedback Shift Register (LFSR).
7. The device of claim 6 , wherein the LFSR performs a polynomial multiplication.
8. The device of claim 6 , wherein the LFSR performs a polynomial division.
9. The device of claim 1 , wherein the device is part of a communication system or a data storage system.
10. The device of claim 1 , wherein the device is part of a digital rights management system.
11. An n-valued shift register with feedback to process n-valued symbols with n>2, wherein each n-valued symbol is represented by one or more signals, comprising:
a plurality of n-valued shift register elements with a memory device implementing an n-valued feedback logic function that is in a feedback loop;
the memory device that stores a single n-valued non-commutative truth table that is determined by modifying an n-valued commutative truth table with an n-valued inverter, the single n-valued non-commutative truth table implementing the n-valued feedback logic function in the n-valued shift register with feedback and outputting an n-valued symbol in accordance with the single n-valued non-commutative truth table based on n-valued symbols from two n-valued shift register elements in the plurality of shift register elements; and
an output of the n-valued shift register with feedback to output the n-valued symbols, wherein the n-valued shift register with feedback is part of the group consisting of: scrambler, sequence generator, generator of symbols of a code, and a Cyclic Redundancy Check (CRC) coder.
12. The n-valued shift register with feedback of claim 11 , wherein the n-valued commutative truth table is an addition over an n-valued finite field.
13. The n-valued shift register with feedback of claim 12 , wherein n=2p with p>1.
14. The n-valued shift register with feedback of claim 11 , wherein the code is a convolutional code.
15. The n-valued shift register with feedback of claim 11 , wherein the n-valued inverter is a multiplier over the n-valued finite field.
16. The n-valued shift register with feedback of claim 11 , wherein the n-valued inverter is not a multiplier over the n-valued finite field.
17. The n-valued shift register with feedback of claim 11 , wherein an n-valued symbol is represented by a plurality of binary symbols.
18. The n-valued shift register with feedback of claim 11 , wherein the n-valued shift register with feedback is a Linear Feedback Shift Register (LFSR).
19. The n-valued shift register with feedback of claim 18 , wherein the LFSR performs at least one of a polynomial multiplication and a polynomial division.
20. The n-valued shift register with feedback of claim 11 , wherein the n-valued shift register with feedback is part of the group consisting of a data storage system and a communication system.