IP Library Granted Patent US 9,472,484
Granted Patent B2
US 9,472,484 · App. 14/624,526 · Granted Oct 18, 2016

Semiconductor structure having thermal backside core

Inventor: Nathan Perkins (Windsor, CO)
Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
H01L23/3675
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Quick Facts
Patent No.
US 9,472,484
App. No.
14/624,526
Granted
Oct 18, 2016
Kind
B2
Abstract

A semiconductor structure includes a semiconductor substrate having a recess disposed beneath a semiconductor device. The semiconductor structure also includes a thermally conductive core disposed in the recess, and a package substrate including a heat sink. The heat sink is in thermal contact with the thermally conductive core.

Claims (27)

1. A semiconductor structure, comprising:

a semiconductor substrate comprising a first side and a second side;

a recess in the semiconductor substrate, the recess being disposed beneath a semiconductor device, wherein the semiconductor substrate having a first thickness between the semiconductor device and the recess that is less than a second thickness in all other locations between the first side and the second side; and

a thermally conductive core disposed in the recess, wherein a thermal resistance between the first side and the second side in the other locations between the first side and the second side is substantially less than a thermal resistance through the first thickness and a lower side of the thermally conductive core.

2. A semiconductor structure as claimed in claim 1 , further comprising a package substrate comprising a heat sink, wherein the heat sink is in thermal contact with the thermally conductive core.

3. A semiconductor structure as claimed in claim 1 , wherein the first thickness is substantially less than the second thickness.

4. A semiconductor structure as claimed in claim 1 , wherein the thermally conductive core is attached to an upper surface of the recess on one side, and to an upper surface of the heat sink on a second side.

5. A semiconductor structure as claimed in claim 1 , further comprising a backside ground plane disposed over a surface of the recess, wherein the thermally conductive core is attached directly to the backside ground plane.

6. A semiconductor structure as claimed in claim 5 , further comprising a die attach material disposed between a lower surface of the semiconductor substrate and an upper surface of the package substrate.

7. A semiconductor structure as claimed in claim 6 , wherein the die attach material is disposed between a lower surface of the thermally conductive core and the heat sink.

8. A semiconductor structure as claimed in claim 5 , further comprising a die attach material disposed on at least one side of the recess.

9. A semiconductor structure as claimed in claim 1 , wherein the thermally conductive core is attached directly to the heat sink.

10. A semiconductor structure as claimed in claim 9 , further comprising a die attach material disposed between a lower surface of the semiconductor substrate and an upper surface of the package substrate.

11. A semiconductor structure as claimed in claim 9 , further comprising a die attach material disposed on at least one side of the recess.

12. A semiconductor structure as claimed in claim 9 , further comprising a die attach material disposed between an upper surface of the thermally conductive core and an upper surface of the recess.

13. A semiconductor structure as claimed in claim 1 , wherein the semiconductor device comprises a power amplifier comprising the semiconductor die, the semiconductor die comprising one or more of gallium arsenide (GaAs), indium phosphide (InP), aluminum arsenide (AlAs), or alloys of GaAs, InP, AlAs.

14. A semiconductor structure as claimed in claim 13 , wherein at least one of the semiconductor die comprises an active semiconductor device.

15. A semiconductor structure as claimed in claim 14 , wherein the active device comprises one or more of a metal-semiconductor field effect transistor (MESFET), a high electron mobility transistor (HEMT), a pseudomorphic HEMT, a junction gate field effect transistor (JFET), and a heterojunction bipolar transistor (HBT).

16. A semiconductor structure as claimed in claim 1 , wherein the semiconductor substrate is electrically insulating.

17. A semiconductor structure as claimed in claim 1 , wherein the semiconductor substrate comprises a material having a comparatively large thermal resistivity.

18. A semiconductor structure as claimed in claim 1 , wherein the recess has a width in the range of approximately 100 μm to approximately 300 μm.

19. A semiconductor structure as claimed in claim 1 , wherein the recess has a width in the range of approximately 100 μm to approximately 1000 μm.

20. A semiconductor structure as claimed in claim 1 , wherein the recess has a width in the range of approximately 100 μm to approximately 300 μm.

21. A semiconductor structure as claimed in claim 1 , wherein the semiconductor substrate has a thickness, and the recess has a depth of approximately 30% to approximately 90% of the thickness of semiconductor substrate.

22. A semiconductor structure as claimed in claim 1 , wherein a portion of the semiconductor substrate in a region between the recess and an upper surface of the semiconductor substrate has a thickness of approximately 70% to approximately 10% of a thickness of the semiconductor substrate.

23. A semiconductor structure as claimed in claim 22 , wherein the thickness of the portion is approximately 20 μm to approximately 20 μm.

24. A semiconductor structure as claimed in claim 22 , wherein the thickness of the portion is approximately 30 μm to approximately 100 μm.

Assignments (5)
CORRECTIVE ASSIGNMENT TO CORRECT THE EXECUTION DATE PREVIOUSLY RECORDED AT REEL: 047422 FRAME: 0464. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Mar 6, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 048883/0702 →
MERGER Recorded Oct 5, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047422/0464 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 17, 2015
From: PERKINS, NATHAN
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 034976/0228 →
Continuity (1)
Related Publication 20160240454A1 · Aug 18, 2016