Vertical memory cell with non-self-aligned floating drain-source implant

1. A memory cell, comprising:

a semiconductor substrate having a trench;

a selection gate extending in the trench in the substrate;

a floating gate on the substrate;

a control gate on the floating gate;

an electrically floating doped region implanted at an intersection of a vertical channel region extending along the selection gate and a horizontal channel region extending along the floating gate, the floating gate overlapping the electrically floating doped region and a portion of the selection gate by a non-zero overlap distance.

2. The memory cell according to claim 1 wherein the trench is covered with a dielectric layer comprising a thicker region near a surface of the substrate, and the floating gate comprises a protuberance which extends beneath the surface of the substrate in the thicker region of the dielectric layer and has a face opposite a portion of the selection gate.

3. The memory cell according to claim 1 , comprising an embedded layer that forms a collective source plane for collecting programming currents and configured to program the memory cell.

4. The memory cell according to claim 1 wherein the substrate includes an indentation, and the electrically floating doped region is spaced from the selection gate by the indentation.

5. The memory cell according to claim 4 wherein a portion of the floating gate extends in to the indentation.

6. The memory cell according to claim 4 , further comprising:

a dielectric layer between the substrate and the floating gate, a portion of the dielectric layer extending in to the indentation.

7. A device, comprising:

a semiconductor substrate having a trench;

a plurality of memory cells arranged in pairs of memory cells, each pair of memory cells including:

a shared selection gate extending in the trench in the substrate;

first and second control gates;

first and second floating gates on the substrate, the first and second control gates being on the first and second floating gates, respectively, the first and second floating gates overlapping a portion of the shared selection gate by a non-zero overlap distance; and

first and second electrically floating doped regions, the first electrically floating doped regions being implanted at a first intersection of a first vertical channel region extending along a first side of the selection gate and a first horizontal channel region extending along the first floating gate, the second electrically floating doped region being implanted at a second intersection of a second vertical channel region extending along a second side of the selection gate and a second horizontal channel region extending along the second floating gate.

8. The device of claim 7 , further comprising a memory circuit in the substrate, the memory circuit including the plurality of memory cells, the plurality of memory cells being arranged in a memory array.

9. The device of claim 8 wherein the memory circuit includes a control circuit configured to program the plurality of memory cells, and configured to apply electric potentials to the substrate, to the shared selection gate, to the first or second control gate, and to drain and source regions, so that hot electrons are injected into the first or second floating gate.

10. The device of claim 7 wherein the trench is covered with a dielectric layer including a thicker region near a surface of the substrate, and each of the first and second floating gates include a protuberance that extends beneath the surface of the substrate in the thicker region of the dielectric layer and has a face opposite a portion of the shared selection gate.

11. The device of claim 10 wherein the memory circuit includes a control circuit configured to erase each memory cell of the plurality of memory cells by tunnel effect, and configured to apply electric potentials to the shared selection gate and the first or second control gate, so that electric charges are extracted from the first or second floating gate and collected by the shared selection gate through the protuberance of the first or second floating gate and the dielectric material extending between the protuberance of the first or second floating gate and the shared selection gate.

12. The device of claim 7 , wherein the first and second floating gates overlap the first and second electrically floating doped regions, respectively.

13. The device of claim 7 , wherein the substrate includes first and second indentations, the first and second electrically floating doped regions being spaced from the shared selection gate by the first and second indentations, respectively.

14. The device of claim 7 , wherein each pair of memory cells further include first and second drain regions in the substrate, the first and second electrically floating doped regions being positioned between the first and second drain regions.

15. A device, comprising:

a semiconductor substrate having a trench;

a first memory cell on the substrate on a first side of the trench and a second memory cell on the substrate on a second side of the trench, each memory cell including:

a selection gate positioned in the trench;

a floating gate on the substrate and on a portion of the selection gate;

a control gate on the floating gate; and

a first indentation in the substrate at a boundary of the first side of the trench and the substrate and a second indentation in the substrate at a boundary of the second side of the trench and the substrate, a portion of each floating gate extending into the first or second indentation; and

first and second doped regions implanted in the substrate, the first and second doped regions being positioned adjacent to the first and second indentations, respectively, the floating gate overlapping the first or second doped region.

16. The device of claim 15 wherein the floating gate overlaps the selection gate with a non-zero overlap distance.

17. The device of claim 15 , further comprising third and fourth doped regions implanted in the substrate, the third and fourth doped regions being spaced lateral to the first and second doped regions, respectively.

18. The device of claim 17 wherein the first, second, third, and fourth doped regions have a first conductivity type, and the first, second, third, and fourth doped region are implanted in a portion of the substrate having a second conductivity type.