IP Library Granted Patent US 9,166,040
Granted Patent B2
US 9,166,040 · App. 14/626,223 · Granted Oct 20, 2015

Semiconductor device

Inventors: Takashi Okawa (Nisshin, JP); Hiroomi Eguchi (Seto, JP); Hiromichi Kinpara (Seto, JP); Satoshi Ikeda (Toyota, JP)
Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
H01L29/7816H01L29/1095
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Quick Facts
Patent No.
US 9,166,040
App. No.
14/626,223
Granted
Oct 20, 2015
Kind
B2
Abstract

A semiconductor device disclosed herein is provided with: a source electrode; a gate electrode; a drain electrode; a first region of a first conductivity type formed in a range exposed at an upper surface of the semiconductor substrate a second region of a second conductivity type; a third region of the first conductivity type; and a fourth region of the first conductivity type. The fourth region includes: a first drift region formed in a range exposed at the upper surface; a second drift region having a first conductivity type impurity concentration higher than that of the first drift region, and adjacent to the first drift region; and a low concentration drift region having a first conductivity type impurity concentration lower than that of the first drift region. The first drift region is projected to a second region side than the second drift region.

Claims (19)

1. A semiconductor device comprising:

a source electrode;

a gate electrode;

a drain electrode;

a first region of a first conductivity type formed in a range exposed at an upper surface of a semiconductor substrate, and making contact with the source electrode;

a second region of a second conductivity type formed in a range exposed at the upper surface, adjacent to the first region, and facing the gate electrode through a gate insulating layer;

a third region of the first conductivity type formed in a range exposed at the upper surface, and making contact with the drain electrode; and

a fourth region of the first conductivity type formed in a range exposed at the upper surface, formed between the second region and the third region, and comprising:

a first drift region formed in a range exposed at the upper surface between the second region and the third region;

a second drift region having a first conductivity type impurity concentration higher than that of the first drift region, and adjacent to the first drift region positioned between the second region and the third region; and

a low concentration drift region having a first conductivity type impurity concentration lower than that of the first drift region, and formed between the second region and the second drift region,

wherein both of the first drift region and the second drift region are adjacent to the third region, and

the first drift region is projected to a second region side than the second drift region.

2. The semiconductor device as in claim 1 , wherein

the second drift region is formed on a far side from the upper surface of the semiconductor substrate than the first drift region.

3. The semiconductor device as in claim 1 , wherein

the second drift region is formed on a lateral side of the first drift region in a plane which is parallel to the upper surface of the semiconductor substrate.

4. The semiconductor device as in claim 1 , wherein

the first drift region is adjacent to the second region.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 1, 2020
From: TOYOTA JIDOSHA KABUSHIKI KAISHA
To: DENSO CORPORATION
Reel/Frame 052285/0419 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 19, 2015
From: OKAWA, TAKASHI; EGUCHI, HIROOMI; KINPARA, HIROMICHI; IKEDA, SATOSHI
To: TOYOTA JIDOSHA KABUSHIKI KAISHA
Reel/Frame 034985/0665 →
Priority Claims (1)
JP 2014-034863 · Feb 26, 2014 · national
Continuity (1)
Related Publication 20150243778A1 · Aug 27, 2015