Optimal factoring of FIR filters
A method and system for the design and implementation of an optimally factored filter is presented. Pairs of angle values are organized in pairing candidates and a threshold is defined to indicate an upper bound on the number of pairing candidates. A first pairing candidate is exchanged above the threshold with a second pairing candidate below the threshold and a matrix is generated based on the pairing candidates below the threshold. A lowest predicted total quantization cost between all pairing candidates represented within the matrix is determined and the pairing candidates that result in the lowest predicted total quantization cost are used to determine the coefficients of the filter.
1. A finite impulse response (FIR) filter, implemented in hardware, configured to receive an input signal and generate an output signal, the filter comprising:
a plurality of first stages, each stage of the plurality of first stages having an order of four or greater; and
one or more second stages, each stage of the one or more second stages having an order less than four,
wherein the one or more second stages and the plurality of first stages are coupled together in cascade and wherein a total order of the plurality of first stages is higher than a total order of the one or more second stages, and
wherein at least one of the plurality of first stages comprises a pairing of two 2 nd order factors to make a 4 th order factor, and
wherein at least one of plurality of first stages includes a stage having a coefficient that is not any one of 1, 0, or −1.
2. The filter of claim 1 , wherein each stage of the plurality of first stages includes at least two multipliers.
3. The filter of claim 1 , further comprising a multiplier positioned at the end of a last stage in the cascade.
4. The filter of claim 1 , further comprising a scaling multiplier disposed between a pair of stages in the cascade.
5. The filter of claim 4 , wherein the scaling multiplier is configured to multiply a signal received at the scaling multiplier by a power of two.
6. The filter of claim 5 , wherein the scaling multiplier is further configured to shift a number of bits associated with an output of a previous stage to the right if the power of two is less than 1, and to shift the number of bits associated with the output of the previous stage to the left if the power of two is greater than 1.
7. The filter of claim 4 , wherein a value of the scaling multiplier is chosen to bring a DC gain of a transfer function representing all previous stages closer to 1.
8. The filter of claim 1 , further comprising a register or delay block located after one or more stages within the cascade.
9. The filter of claim 1 , wherein the filter is a digital filter.
10. The filter of claim 1 , wherein the filter is an analog filter.
11. The filter of claim 1 , wherein each stage of the plurality of first stages is not identical to each other.
12. The filter of claim 1 , wherein each of the 2 nd order factors has roots representing a pair of complex-conjugate numbers lying on a unit circle in a complex plane.