Apparatus and method for combining multiple charge pumps in phase locked loops

1. A frequency synthesizer comprising:

circuitry configured to

generate two or more feedback clocks based on oscillation signals output from a voltage-controlled oscillator;

modulate the two or more feedback clocks based on fractional offsets from a reference clock frequency for input into a plurality of phase and frequency detectors (PFDs) driving a plurality of charge pumps; and

select an output from one of the plurality of PFDs corresponding to an early feedback clock input that leads a reference clock or a late feedback clock input that lags the reference clock to drive each of the plurality of charge pumps,

wherein the circuitry is further configured to randomize selections of the plurality of charge pumps associated with the early feedback clock and late feedback clock.

2. The frequency synthesizer of claim 1 , wherein the circuitry is further configured to select the early feedback clock or the late feedback clock to drive the plurality of charge pumps based on a calculated phase residue output from a sigma-delta modulator.

3. The frequency synthesizer of claim 1 , wherein a net charge of the currents output from the plurality of charge pumps is equal to zero.

4. The frequency synthesizer of claim 1 , wherein

an amount of fractional offset corresponds to a quantity of charge pumps; and

the circuitry is configured to incrementally step through one or more phases of the early feedback clock and the late feedback clock at a rate based on the amount of fractional offset.

5. The frequency synthesizer of claim 4 , wherein the amount of fractional offset is equal to 1/16 and quantity of charge pumps is equal to sixteen.

6. The frequency synthesizer of claim 1 , wherein the circuitry is further configured to modulate an integer part and a fractional part of the fractional offsets.

7. The frequency synthesizer of claim 6 , wherein the circuitry is further configured to generate clock edges for the two or more feedback clocks at phases corresponding to the fractional offsets.

8. The frequency synthesizer of claim 7 , wherein the circuitry is further configured to modulate between one or more integer values indicating a number of selected charge pumps.

9. The frequency synthesizer of claim 1 , wherein the circuitry is further configured to delay one or more of the feedback clocks by a number of the oscillation signals output from the voltage-controlled oscillator.

10. The frequency synthesizer of claim 1 , wherein the two or more charge pumps and the two or more phase and frequency detectors operate in linear gain regions.

11. The frequency synthesizer of claim 1 , wherein the circuitry is further configured to filter signals output from the plurality of charge pumps based on an amount of phase noise present in the oscillation signals output from the voltage-controlled oscillator.

12. The frequency synthesizer of claim 1 , wherein a sum of outputs from the plurality of charge pumps corresponds to a weighted offset between one or more charge pumps driven by the early feedback clock and one or more charge pumps driven by the late feedback clock.

13. The frequency synthesizer of claim 1 , wherein the circuitry is further configured to select the early feedback clock or the late feedback clock to drive the plurality of charge pumps based on a predetermined number of additional bits retained in an integer phase output of a sigma-delta modulator indicating a first number of charge pumps driven by the early feedback clock and a second number of charge pumps driven by the late feedback clock.

14. The frequency synthesizer of claim 13 , wherein four additional bits are retained in the integer phase output of the sigma-delta modulator to indicate the first number of charge pumps driven by the early feedback clock and the second number of charge pumps driven by the late feedback clock.

15. A frequency synthesizer comprising:

circuitry configured to

generate two or more feedback clocks based on oscillation signals output from a voltage-controlled oscillator;

modulate the two or more feedback clocks based on fractional offsets from a reference clock frequency for input into a plurality of phase and frequency detectors (PFDs) driving a plurality of charge pumps; and

toggle between an early feedback clock and a late feedback clock driving the plurality of charge pumps based on a feedback clock selector signal.

16. The frequency synthesizer of claim 15 , wherein the circuitry is further configured to randomize selection of the early feedback clock and the late feedback clock.

17. The frequency synthesizer of claim 15 , wherein the circuitry is further configured to randomize selections of the plurality of charge pumps driven by the early feedback clock or the late feedback clock.

18. The frequency synthesizer of claim 15 , wherein the circuitry is further configured to reset outputs of the plurality of PFDs via a delayed feedback clock signal associated with each of the early feedback clock and the late feedback clock.

19. A frequency synthesizer comprising:

circuitry configured to

generate two or more feedback clocks based on oscillation signals output from a voltage-controlled oscillator;

modulate the two or more feedback clocks based on fractional offsets from a reference clock frequency for input into a plurality of phase and frequency detectors (PFDs) driving a plurality of charge pumps; and

modulate an early feedback clock and a late feedback clock at equal and opposite phase and frequency offsets from a center frequency.