Semiconductor device and data processing system selectively operating as one of a big endian or little endian system
The present invention is to provide a semiconductor device that can correctly switch endians on the outside even if the endian of a parallel interface is not recognized on the outside. The semiconductor device includes a switching circuit and a first register. The switching circuit switches between whether a parallel interface with the outside is to be used as a big endian or a little endian. A first register holds control data of the switching circuit. The switching circuit regards the parallel interface as the little endian when first predetermined control information, that is unchanged in the values of specific bit positions even if its high-order and low-order bit positions are transposed, is supplied to the first register, and regards the parallel interface as the big endian when second predetermined control information, that is unchanged in the values of specific bit positions even if its high-order and low-order bit positions are transposed, is supplied to the first register. Whatever the endian setting status, the control information can be correctly inputted without being influenced by the endian setting status.
1. A semiconductor device including a processing unit and a plurality of data terminals, the processing unit comprising:
an interface circuit configured to receive an endian setting command from the plurality of data terminals; and
an endian setting register configured to store the endian setting command,
wherein the interface circuit is configured to switch operation between a big endian mode and a little endian mode based on a value of the endian setting command stored in the endian setting register,
wherein the endian setting command is comprised of a high-order bit portion and a low-order bit portion, and
wherein the high-order bit portion and the low-order bit portion of the endian setting command are identical.
2. A semiconductor device according to claim 1 , further comprising:
a data bus configured to transfer the endian setting command from the interface circuit to the endian setting register,
wherein the bit length of each of the high-order bit portion and the low-order bit portion of the endian setting command is a same as the width of the data bus.
3. A semiconductor device according to claim 2 , further comprising:
a gate driver circuit and a source driver circuit configured to output display data to a liquid crystal display panel.
4. A semiconductor device including a processing unit and a plurality of data terminals, the processing unit comprising:
an interface circuit configured to receive an endian setting command and an endian setting address from the plurality of data terminals; and
an endian setting register corresponding to the endian setting address and configured to store the endian setting command,
wherein the interface circuit is configured to switch operation between a big endian mode and a little endian mode based on a value of the endian setting command stored in the endian setting register,
wherein each of the endian setting command and the endian setting address is comprised of a high-order bit portion and a low-order bit portion,
wherein the high-order bit portion and the low-order bit portion of the endian setting command are identical, and
wherein the high-order bit portion and the low-order bit portion of the endian setting address are identical.
5. A semiconductor device according to claim 4 , further comprising:
a data bus configured to transfer the endian setting command from the interface circuit to the endian setting register,
wherein the bit length of each of the high-order bit portion and the low-order bit portion of the endian setting command is a same as the width of the data bus of the processing unit, and
wherein the bit length of each of the high-order bit portion and the low-order bit portion of the endian setting address is a same as the width of the data bus of the processing unit.
6. A semiconductor device according to claim 5 , further comprising:
a gate driver circuit and a source driver circuit configured to output display data to a liquid crystal display panel.
7. A semiconductor device including a processing unit and a data input, the processing unit comprising:
an interface circuit configured to receive an endian setting command and an endian setting address from the data input; and
an endian setting register configured to store the endian setting command,
wherein the interface circuit is configured to switch operation between a big endian mode and a little endian mode based on a value of the endian setting command stored in the endian setting register,
wherein the endian setting command is comprised of a high-order bit portion and a low-order bit portion, and
wherein the high-order bit portion and the low-order bit portion of the endian setting command are identical.
8. A semiconductor device according to claim 7 , further comprising:
a data bus configured to transfer the endian setting command from the interface circuit to the endian setting register,
wherein the bit length of each of the high-order bit portion and the low-order bit portion of the endian setting command is a same as the width of the data bus.
9. A semiconductor device according to claim 8 , further comprising:
a gate driver circuit and a source driver circuit configured to output display data to a liquid crystal display panel.
10. A semiconductor device including a processing unit and a data input, the processing unit comprising:
an interface circuit configured to receive an endian setting command and an endian setting address from the data input; and
an endian setting register corresponding to the endian setting address and configured to store the endian setting command,
wherein the interface circuit is configured to switch operation between a big endian mode and a little endian mode based on a value of the endian setting command stored in the endian setting register,
wherein each of the endian setting command and the endian setting address is comprised of a high-order bit portion and a low-order bit portion,
wherein the high-order bit portion and the low-order bit portion of the endian setting command are identical, and
wherein the high-order bit portion and the low-order bit portion of the endian setting address are identical.
11. A semiconductor device according to claim 10 , further comprising:
a data bus configured to transfer the endian setting command from the interface circuit to the endian setting register,
wherein the bit length of each of the high-order bit portion and the low-order bit portion of the endian setting command is a same as the width of the data bus, and
wherein the bit length of each of the high-order bit portion and the low-order bit portion of the endian setting address is a same as the width of the data bus of the display driver.
12. A semiconductor device according to claim 11 , further comprising:
a gate driver circuit and a source driver circuit configured to output display data to a liquid crystal display panel.