Clock domain crossing serial interface
View Patent ↗A method for serial interface clock domain crossing includes identifying a data communication command received over a serial interface. An address is decoded to determine whether the address falls within a direct latch address range of a register bank. Data is communicated over the serial interface. A multiplexed output clock is generated, for writing to and reading from the register bank, based on at least one of a current system operating state and a refresh control signal from a host processor.
1. A method for serial interface clock domain crossing, the method comprising:
identifying a data communication command received over a serial interface;
decoding an address to determine whether the address falls within a direct latch address range of a register bank;
communicating data over the serial interface; and
generating a multiplexed output clock using a system clock and a Power Management Unit (PMU) clock, for writing to and reading from the register bank, based on at least one of a current system operating state and a refresh control signal from a host processor.
2. The method of claim 1 , further comprising accounting for a clock domain crossing in association with communicating the data.
3. The method of claim 2 , further comprising when the address falls within the direct latch address range, directly latching the data into a direct latch register of the register bank based on a clock signal of the serial interface.
4. The method of claim 1 , further comprising:
accounting for a clock domain crossing in association with communicating the data; and
when the address does not fall within the direct latch address range, storing the data into a first-in-first-out (FIFO) register.
5. The method of claim 4 , further comprising writing data from the FIFO register to the register bank.
6. The method of claim 1 , further comprising, when the data communication command comprises a read command, communicating the data over the serial interface after a wait time.
7. The method of claim 1 , further comprising, when the data communication command comprises a write command, communicating the data over the serial interface for writing to the register bank.
8. The method of claim 1 , further comprising, after a wait time, communicating a response code over the serial interface.
9. The method of claim 1 , further comprising, when the data communication command comprises a write command and the address does not fall within the direct latch address range, determining whether a first-in-first-out (FIFO) register is full.
10. The method of claim 9 , further comprising, when determination is made that the FIFO register is full, communicating a write error response code.
11. The method of claim 1 , further comprising, when the data communication command comprises a read command and the address overlaps with data in a first-in-first-out (FIFO) register waiting to be written to the register bank, communicating a read error response code.
12. A system for serial interface clock domain crossing, the system comprising:
a communications interface configured to identify a data communication command received over a serial interface;
register control circuitry configured to:
decode an address to determine whether the address falls within a direct latch address range of a register bank;
communicate data over the serial interface; and
a clock multiplexer configured to generate a multiplexed output clock using a system clock and a Power Management Unit (PMU) clock, for writing to and reading from the register bank, based on at least one of a current system operating state and a system refresh control signal from a host processor.
13. The system of claim 12 , wherein the register control circuit is further configured to:
account for a clock domain crossing in association with data communication over the serial interface; and
directly latch the data into a direct latch register of the register bank based on a clock signal of the serial interface when the address falls within the direct latch address range.
14. The system of claim 12 , wherein the register control circuit is further configured to account for a clock domain crossing in association with data communication over the serial interface.
15. The system of claim 12 , wherein the register control circuit is further configured to store the data into a first-in-first-out (FIFO) register when the address does not fall within the direct latch address range.
16. The system of claim 12 , wherein the clock multiplexer is configured to multiplex between a clock of the serial interface and the system clock.
17. A method, comprising:
receiving a data communication command and an address over a serial interface and determining that the data communication command comprises one of a read or a write command;
resolving the address to access a register bank;
decoding the address received over the serial interface to determine whether the address falls within a direct latch address range of the register bank;
when the address does not fall within the direct latch address range of the register bank, storing data into a first-in-first-out (FIFO) register if the FIFO register is not full; and
after a wait time, communicating a response code including a status indicator over the serial interface.
18. The method of claim 17 , further comprising, communicating the data over the serial interface.
19. The method of claim 17 , further comprising accounting for a clock domain crossing when directly latching the data into a direct latch register of the register bank based on a clock signal of the serial interface.
20. The method of claim 17 , further comprising, when the FIFO register is full, communicating a write error response code.