Semiconductor integrated circuit
View Patent ↗A semiconductor integrated circuit includes a power supply switch circuit which uses a PMOS transistor and an NMOS transistor to select a first power supply voltage applied to a first power supply input terminal or a second power supply voltage applied to a second power supply input terminal, and output the selected voltage as a power supply voltage to a third power supply output terminal, a first switch control circuit connected to the gate of the PMOS transistor, and a second switch control circuit connected to the gate of the NMOS transistor.
1. A semiconductor integrated circuit comprising:
a ground terminal configured to receive a ground potential;
a first power supply terminal configured to receive a first power supply voltage higher than the ground potential;
a second power supply terminal configured to receive a second power supply voltage higher than the ground potential and lower than the first power supply voltage;
a third power supply terminal configured to output the first power supply voltage received by the first power supply terminal or the second power supply voltage received by the second power supply terminal;
a first PMOS transistor configured to connect the first and third power supply terminals together;
a first NMOS transistor configured to connect the second and third power supply terminals together;
a first switch control circuit connected to the first PMOS transistor; and
a second switch control circuit connected to the first NMOS transistor,
wherein
the first switch control circuit outputs a signal ranging from the level of the ground potential to the level of the first power supply voltage to a gate of the first PMOS transistor, to control the first PMOS transistor so that the first PMOS transistor is on or off, and
the second switch control circuit outputs a signal ranging from the level of the ground potential to the level of the first power supply voltage to a gate of the first NMOS transistor, to control the first NMOS transistor so that the first NMOS transistor is on or off.
2. The semiconductor integrated circuit of claim 1 , further comprising:
a discharge circuit configured to connect the third power supply terminal and the ground terminal together.
3. The semiconductor integrated circuit of claim 2 , wherein
the first NMOS transistor, the first PMOS transistor, and the discharge circuit are controlled exclusively from each other.
4. The semiconductor integrated circuit of claim 1 , wherein
the first NMOS transistor and the first PMOS transistor are controlled exclusively from each other.
5. The semiconductor integrated circuit of claim 1 , wherein
a substrate electrode of the first PMOS transistor is connected to the first power supply terminal.
6. The semiconductor integrated circuit of claim 1 , wherein
a substrate electrode of the first NMOS transistor is connected to the ground terminal.
7. The semiconductor integrated circuit of claim 1 , further comprising:
a pull-down circuit connected to the gate of the first NMOS transistor and configured to pull the gate voltage of the first NMOS transistor down to the level of the ground potential according to a pull-down control signal.
8. A semiconductor integrated circuit comprising:
a ground terminal configured to receive a ground potential;
a first power supply terminal configured to receive a first power supply voltage higher than the ground potential;
a second power supply terminal configured to receive a second power supply voltage higher than the ground potential and lower than the first power supply voltage;
a third power supply terminal configured to output the first power supply voltage received by the first power supply terminal or the second power supply voltage received by the second power supply terminal;
a first PMOS transistor configured to connect the first and third power supply terminals together;
a second PMOS transistor configured to connect the second and third power supply terminals together;
a first switch control circuit connected to the first PMOS transistor;
a second switch control circuit connected to the second PMOS transistor; and
a substrate control circuit having an output connected to a substrate electrode of the second PMOS transistor,
wherein
the substrate control circuit receives the first and second power supply voltages as power supply, and outputs the higher one of the first and second power supply voltages.
9. The semiconductor integrated circuit of claim 8 , further comprising:
a discharge circuit configured to connect the third power supply terminal and the ground terminal together.
10. The semiconductor integrated circuit of claim 8 , wherein
a substrate electrode of the first PMOS transistor is connected to the output of the substrate control circuit.
11. The semiconductor integrated circuit of claim 8 , wherein
the second switch control circuit outputs a signal ranging from the level of the ground potential to the level of the first power supply voltage to a gate of the second PMOS transistor, to control the second PMOS transistor so that the second PMOS transistor is on or off.
12. The semiconductor integrated circuit of claim 8 , wherein
the second switch control circuit receives a voltage output by the substrate control circuit as power supply, and outputs a signal ranging from the level of the ground potential to the level of the first power supply voltage or a signal ranging from the level of the ground potential to the level of the second power supply voltage, to a gate of the second PMOS transistor, to control the second PMOS transistor so that the second PMOS transistor is on or off.
13. The semiconductor integrated circuit of claim 8 , wherein
the second switch control circuit includes
an input terminal configured to receive an input signal,
an output terminal configured to output an output signal,
a first output circuit configured to output a signal ranging from the level of the ground potential to the level of the first power supply voltage according to the input signal,
a second output circuit configured to output a signal ranging from the level of the ground potential to the level of the second power supply voltage according to the input signal,
a third PMOS transistor configured to connect the first output circuit and the output terminal together, and
a fourth PMOS transistor configured to connect the second output circuit and the output terminal together,
a gate of the third PMOS transistor receives the second power supply voltage, and a substrate electrode of the third PMOS transistor is connected to the output of the substrate control circuit, and
a gate of the fourth PMOS transistor receives the first power supply voltage, and a substrate electrode of the fourth PMOS transistor is connected to the output of the substrate control circuit.
14. The semiconductor integrated circuit of claim 13 , wherein
the second switch control circuit includes
a first pull-down circuit connected to the output terminal and configured to pull the voltage of the output terminal down to the ground potential according to the signal outputted from the first output circuit.
15. The semiconductor integrated circuit of claim 13 , wherein
the second switch control circuit includes
a second pull-down circuit connected to the output terminal and configured to pull the voltage of the output terminal down to the ground potential according to the signal outputted from the second output circuit.
16. The semiconductor integrated circuit of claim 13 , wherein
the second switch control circuit includes
a first pull-up circuit connected to the output terminal and configured to pull the voltage of the output terminal up to the first power supply voltage according to the signal outputted from the first output circuit.
17. The semiconductor integrated circuit of claim 13 , wherein
the second switch control circuit includes
a second pull-up circuit connected to the output terminal and configured to pull the voltage of the output terminal up to the second power supply voltage according to the signal outputted from the second output circuit.
18. A semiconductor integrated circuit comprising:
a ground terminal configured to receive a ground potential;
a first power supply terminal configured to receive a first power supply voltage higher than the ground potential;
a second power supply terminal configured to receive a second power supply voltage higher than the ground potential and lower than the first power supply voltage;
a third power supply terminal configured to output the first power supply voltage received by the first power supply terminal or the second power supply voltage received by the second power supply terminal;
a first PMOS transistor configured to connect the first and third power supply terminals together;
a second PMOS transistor configured to connect the third power supply terminal and a first node together;
a third PMOS transistor configured to connect the first node and the second power supply terminal together;
a first switch control circuit connected to the first PMOS transistor;
a second switch control circuit connected to the second PMOS transistor; and
a third switch control circuit connected to the third PMOS transistor,
wherein
a substrate electrode of the second PMOS transistor is connected to the first power supply terminal,
a substrate electrode of the third PMOS transistor is connected to the second power supply terminal,
the first switch control circuit outputs a signal ranging from the level of the ground potential to the level of the first power supply voltage to a gate of the first PMOS transistor, to control the first PMOS transistor so that the first PMOS transistor is on or off,
the second switch control circuit outputs a signal ranging from the level of the ground potential to the level of the first power supply voltage to a gate of the second PMOS transistor, to control the second PMOS transistor so that the second PMOS transistor is on or off, and
the third switch control circuit outputs a signal ranging from the level of the ground potential to the level of the second power supply voltage to a gate of the third PMOS transistor, to control the third PMOS transistor so that the third PMOS transistor is on or off.
19. The semiconductor integrated circuit of claim 18 , further comprising:
a discharge circuit configured to connect the third power supply terminal and the ground terminal together.
20. The semiconductor integrated circuit of claim 18 , wherein
a substrate electrode of the first PMOS transistor is connected to the first power supply terminal.