IP Library Granted Patent US 9,312,295
Granted Patent B2
US 9,312,295 · App. 14/634,557 · Granted Apr 12, 2016

Semiconductor device and a manufacturing method thereof

Inventors: Takashi Terada (Kanagawa, JP); Shinya Hori (Hitachinaka, JP)
Assignee: RENESAS ELECTRONICS CORPORATION
H01L27/1464H01L27/1463H01L27/14603H01L27/14609H01L27/14623H01L27/14632H01L27/14636H01L27/14643H01L27/14683H01L27/14687H01L27/14689H01L27/14621H01L27/14627
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Quick Facts
Patent No.
US 9,312,295
App. No.
14/634,557
Granted
Apr 12, 2016
Kind
B2
Abstract

A semiconductor device has a chip region including a back-side illumination type photoelectric conversion element, a mark-like appearance part, a pad electrode, and a coupling part. The mark-like appearance part includes an insulation film covering the entire side surface of a trench part formed in a semiconductor substrate. The pad electrode is arranged at a position overlapping the mark-like appearance part. The coupling part couples the pad electrode and mark-like appearance part. At least a part of the pad electrode on the other main surface side of the substrate is exposed through an opening reaching the pad electrode from the other main surface side of the substrate. The mark-like appearance part and coupling part are arranged to at least partially surround the outer circumference of the opening in plan view.

Claims (66)

1. A semiconductor device comprising:

a chip region,

the chip region including:

a semiconductor substrate having main surfaces;

a photoelectric conversion element formed in the semiconductor substrate;

a mark-like appearance part extending from one of the main surfaces of the semiconductor substrate toward the other main surface side opposite to the one main surface, and for applying a light to the photoelectric conversion element;

a pad electrode arranged at a position overlapping the mark-like appearance part on the one main surface side of the semiconductor substrate; and

a coupling part for coupling the pad electrode and the mark-like appearance part,

wherein the mark-like appearance part includes an insulation film covering the entire side surface of a trench part formed in the semiconductor substrate,

wherein at least a part of the pad electrode on the other main surface side is exposed through an opening reaching the pad electrode from the other main surface side of the semiconductor substrate, and

wherein the mark-like appearance part and the coupling part are arranged in such a manner as to surround at least a part of the outer circumference of the opening in plan view.

2. The semiconductor device according to claim 1 ,

wherein the mark-like appearance part penetrates through the semiconductor substrate from the one main surface to the other main surface of the semiconductor substrate.

3. The semiconductor device according to claim 1 ,

wherein the mark-like appearance part and the coupling part are arranged in such a manner as to surround the entire outer circumference of the opening in plan view.

4. The semiconductor device according to claim 1 ,

wherein the mark-like appearance part includes a conductive film arranged inside the insulation film.

5. The semiconductor device according to claim 4 ,

wherein the conductive film is formed of a metal material.

6. The semiconductor device according to claim 1 ,

wherein a seal ring surrounding the photoelectric conversion element and the pad electrode in plan view is arranged at the outermost part in the chip region, and

wherein another mark-like appearance part as the same layer as the the mark-like appearance part is arranged on the other main surface side of the seal ring.

7. The semiconductor device according to claim 1 ,

wherein the photoelectric conversion element is electrically coupled with a wiring layer having a plurality of metal wires, and

wherein at least a part of the coupling part is formed in such a manner as to include the same layer as at least apart of the metal wires.

8. The semiconductor device according to claim 1 ,

wherein a plurality of the chip regions are spaced apart from one another in an array at the semiconductor substrate,

wherein an alignment mark part extending in such a manner as to penetrate through the semiconductor substrate from the one main surface to the other main surface in a dicing region interposed between a pair of the chip regions adjacent to each other, and

wherein the alignment mark part is formed as the same layer as the mark-like appearance part.

9. A method for manufacturing a semiconductor device including a chip region,

the method comprising the steps of:

providing a semiconductor substrate having main surfaces;

forming a photoelectric conversion element in the semiconductor substrate;

forming a trench part extending from one of the main surfaces of the semiconductor substrate toward the other main surface side opposite to the one main surface, and for applying a light to the photoelectric conversion element;

forming an insulation film covering the entire side surface of the trench part, and thereby forming a mark-like appearance part;

forming a coupling part to be coupled with the mark-like appearance part;

forming a pad electrode to be coupled with the coupling part at a position overlapping the the mark-like appearance part on the one main surface side of the semiconductor substrate; and

forming an opening reaching the pad electrode from the other main surface side of the semiconductor substrate in such a manner as to expose at least a part of the other main surface side of the pad electrode,

wherein the mark-like appearance part and the coupling part are formed in such a manner as to surround at least a part of the outer circumference of the opening in plan view.

10. The method for manufacturing a semiconductor device according to claim 9 ,

wherein a plurality of the chip regions each including the photoelectric conversion element and the pad electrode are formed spaced apart from one another in an array in the semiconductor substrate,

the method further comprising a step of forming an alignment mark part extending in such a manner as to penetrate through the semiconductor substrate from the one main surface to the other main surface in a dicing region interposed between a pair of the chip regions adjacent to each other,

wherein a first trench part for forming the alignment mark part is formed simultaneously with a second trench part for forming the mark-like appearance part.

11. The method for manufacturing a semiconductor device according to claim 9 ,

wherein a plurality of the chip regions each including the photoelectric conversion element and the pad electrode are formed spaced apart from one another in an array in the semiconductor substrate,

the method further comprising a step of forming an alignment mark part extending in the direction toward the other main surface from the one main surface in a dicing region interposed between a pair of the chip regions adjacent to each other,

wherein a first trench part for forming the alignment mark part is formed by a different step from that for a second trench part for forming the mark-like appearance part.

12. The method for manufacturing a semiconductor device according to claim 9 ,

wherein the step of forming the mark-like appearance part is performed before the step of forming the photoelectric conversion element, and

wherein the step of forming the mark-like appearance part includes a step of forming a conductive film inside the insulation film.

13. The method for manufacturing a semiconductor device according to claim 9 ,

wherein the step of forming the mark-like appearance part is performed after the step of forming the photoelectric conversion element, and

wherein the step of forming the mark-like appearance part includes a step of forming a conductive film of a metal material inside the insulation film.

14. The method for manufacturing a semiconductor device according to claim 13 ,

the method further comprising a step of forming a conductive film forming a contact conductive layer to be electrically coupled with the photoelectric conversion element,

wherein the step of forming the conductive film of the metal material is performed simultaneously with the step of forming a conductive film forming the contact conductive layer to be electrically coupled with the photoelectric conversion element.

15. The method for manufacturing a semiconductor device according to claim 9 ,

the method further comprising the steps of:

forming a seal ring surrounding the photoelectric conversion element and the pad electrode in plan view at the outermost part of the chip region; and

forming another mark-like appearance part as the same layer as the mark-like appearance part on the other main surface side of the seal ring,

wherein the step of forming the another mark-like appearance part is performed simultaneously with the step of forming an insulation film covering the inner wall surface of the trench part, and thereby forming the mark-like appearance part.

16. The method for manufacturing a semiconductor device according to claim 9 ,

the method further comprising a step of forming a wiring layer including a plurality of stacked metal wires to be electrically coupled with the photoelectric conversion element on the one main surface side of the semiconductor substrate,

wherein at least a part of the step of forming the coupling part is performed simultaneously with the step of forming the wiring layer, and thereby at least a part of the coupling part is formed in such a manner as to include the same layer as at least a part of the metal wires.

17. The method for manufacturing a semiconductor device according to claim 16 ,

wherein the pad electrode is formed as the same layer as the metal wire other than the metal wire at the layer most distant from the one main surface of the stacked metal wires.

Assignments (3)
CHANGE OF ADDRESS Recorded Nov 29, 2017
From: RENESAS ELECTRONICS CORPORATION
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 044928/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NAME OF THE FIRST ASSIGNOR PREVIOUSLY RECORDED ON REEL 037383 FRAME 0156. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Mar 29, 2016
From: TERADA, TAKASHI; HORI, SHINYA
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 038298/0921 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 30, 2015
From: TERADA, TAKESHI; HORI, SHINYA
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 037383/0156 →
Priority Claims (1)
JP 2014-038447 · Feb 28, 2014 · national
Continuity (1)
Related Publication 20150249102A1 · Sep 3, 2015