Semiconductor memory device
View Patent ↗A semiconductor memory device includes a first portion including a semiconductor element, a second portion surrounding the semiconductor element. The second portion includes a stack of conductive layers and insulating layers, and at least one groove through the conductive layers and the insulating layers.
1. A semiconductor memory device comprising:
a first portion including a semiconductor element; and
a second portion surrounding the semiconductor element,
wherein the second portion includes:
a stack of conductive layers and insulating layers, and
at least one groove through the conductive layers and the insulating layers, the at least one groove including a first groove having a single hollow portion, wherein the single hollow portion extends in a stacking direction of the stack of conductive layers and insulating layers and extends through multiple layers of the stack.
2. The device according to claim 1 ,
wherein the at least one groove extends in a stacking direction of the stack of conductive layers and insulating layers.
3. The device according to claim 2 ,
wherein the at least one groove includes the first groove extending through the conductive layers and the insulating layers and a second groove that is farther from the semiconductor element than the first groove, extending through the conductive layers and the insulating layers.
4. The device according to claim 1 ,
wherein the single hollow portion is partially filled with insulating material.
5. The device according to claim 1 ,
wherein the semiconductor element includes a memory cell array.
6. The device according to claim 5 ,
wherein the semiconductor element further includes a peripheral circuit for the memory cell array.
7. The device according to claim 1 ,
the second portion further includes a metal layer and a metal pillar.
8. The device according to claim 7 , wherein
the stack and the at least one groove are farther from the semiconductor element than the metal layer and the metal pillar.
9. The device according to claim 1 , wherein
the second portion further includes metal layers stacked directly above and directly below the stack, and metal pillars that extend through the metal layers.
10. A semiconductor memory device comprising:
a first portion including a semiconductor element; and
a second portion partially surrounding the semiconductor element,
wherein the second portion includes:
a stack of conductive layers and insulating layers, and
at least one groove through the conductive layers and the insulating layers, the at least one groove including a first groove having a single hollow portion, wherein the single hollow portion extends in a stacking direction of the stack of conductive layers and insulating layers and extends through multiple layers of the stack.
11. The device according to claim 10 ,
wherein the semiconductor element includes a memory cell array and a peripheral circuit for the memory cell array, and the second portion surrounds the semiconductor element alongside the memory cell array but not alongside a substantial portion of the peripheral portion.
12. The device according to claim 10 ,
wherein the semiconductor element has a rectangular shape, and the second portion surrounds the semiconductor element alongside corners of the semiconductor element but not alongside a substantial portion of each side of the semiconductor element.
13. The device according to claim 10 ,
wherein the at least one groove extends in a stacking direction of the stack of conductive layers and insulating layers.
14. The device according to claim 10 ,
the second portion further includes a metal layer and a metal pillar, and the stack and the at least one groove are farther from the semiconductor element than the metal layer and the metal pillar.
15. The device according to claim 10 , wherein
the second portion further includes metal layers stacked directly above and directly below the stack, and metal pillars that extend through the metal layers.
16. A semiconductor memory device comprising:
a first portion including a semiconductor element; and
a second portion surrounding the semiconductor element,
wherein the second portion includes:
a stack of conductive layers and insulating layers,
at least one groove that is formed through multiple layers of the stack and to extend in a stacking direction of the stack such that a sidewall of the at least one groove is in direct contact with the conductive and insulating layers of the stack, and
an insulating film that covers the sidewall of the groove so as to separate a hollow portion of the groove and the conductive and insulating layers of the stack.
17. The device according to claim 16 , wherein the hollow portion of the groove extends from an upper portion of the stack to a lower portion of the stack to span multiple conductive and insulating layers of the stack.