Semiconductor storage device with smaller driving force precharge
A semiconductor storage device includes an SRAM memory cell composed of a drive transistor, a transfer transistor and a load transistor, an I/O circuit that is connected to bit lines connected to the memory cell, and an operating mode control circuit that switches an operating mode of the I/O circuit between a resume standby mode and a normal operation mode, wherein the I/O circuit includes a write driver that writes data to bit lines, a sense amplifier that reads data from the bit lines, a first switch inserted between the bit lines and the write driver, a second switch inserted between the bit lines and the sense amplifier, a precharge circuit that precharges the bit lines, and a control circuit that controls the first and second switches and the precharge circuit according to a signal from the operating mode control circuit.
1. A semiconductor storage device comprising:
an SRAM memory cell that is composed of a drive transistor, a transfer transistor and a load transistor;
an I/O circuit that is connected to bit lines connected to the memory cell; and
an operating mode control circuit that switches an operating mode of the I/O circuit between a resume standby mode and a normal operation mode, wherein
the I/O circuit includes:
a write driver that writes data to the bit lines,
a sense amplifier that reads data from the bit lines,
a first switch that is inserted between the bit lines and the write driver,
a second switch that is inserted between the bit lines and the sense amplifier,
a precharge circuit that precharges the bit lines, and
a control circuit that controls the first and second switches and the precharge circuit according to a signal from the operating mode control circuit, and
the control circuit turns off the first and second switches and the precharge circuit in the resume standby mode, and causes the precharge circuit to precharge the bit lines with a smaller driving force compared with in the normal operation mode when returning from the resume standby mode to the normal operation mode.
2. The semiconductor storage device according to claim 1 , wherein
the precharge circuit includes:
a first precharge circuit that precharges the bit lines in the normal operation mode, and
a second precharge circuit that has a smaller driving force than the first precharge circuit and precharges the bit lines, and
the control circuit causes the second precharge circuit to precharge the bit lines when returning from the resume standby mode to the normal operation mode.
3. The semiconductor storage device according to claim 2 , wherein
the control circuit turns off the second precharge circuit after precharge of the bit lines is completed, and causes the first precharge circuit to precharge the bit lines in the subsequent normal operation mode.
4. The semiconductor storage device according to claim 1 , wherein
the operating mode control circuit supplies a power supply potential to the precharge circuit, and
when returning from the resume standby mode to the normal operation mode, the operating mode control circuit reduces the power supply potential supplied to the precharge circuit compared with in the normal operation mode.
5. The semiconductor storage device according to claim 4 , wherein
the operating mode control circuit raises the power supply potential supplied to the precharge circuit to a potential used in the normal operation mode after precharge of the bit lines is completed.
6. The semiconductor storage device according to claim 1 , comprising:
a source potential control circuit that is connected to a source line connected to a source of the drive transistor and supplies a potential to the source line, wherein
the source potential control circuit sets a potential of the source line at a ground potential in the normal operation mode, and sets a potential of the source line at a potential higher than the ground potential in the resume standby mode.
7. The semiconductor storage device according to claim 1 , comprising:
a word line driver that drives a word line connected to the memory cell, wherein
the word line driver includes:
a driver circuit that supplies a potential to the word line,
a power supply line of the driver circuit,
a first power supply switch that is inserted between the power supply line and a power supply,
a second power supply switch that is inserted between the power supply line and a power supply and has a smaller driving force than the first power supply switch, and
a control signal generation circuit that supplies a control signal to the first and second power supply switches, and
the control signal generation circuit closes the first power supply switch and opens the second power supply switch in the normal operation mode, opens the first and second power supply switches in the resume standby mode, and opens the first power supply switch and closes the second power supply switch when returning from the resume standby mode to the normal operation mode.
8. The semiconductor storage device according to claim 7 , wherein
the control signal generation circuit closes the first power supply switch and opens the second power supply switch after the word line reaches a power supply potential.