IP Library Granted Patent US 9,298,531
Granted Patent B1
US 9,298,531 · App. 14/635,361 · Granted Mar 29, 2016

Watchdog timer with mode dependent time out

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Quick Facts
Patent No.
US 9,298,531
App. No.
14/635,361
Granted
Mar 29, 2016
Kind
B1
Abstract

A method and apparatus to operate a watchdog timer having a first time out period in a processing system. The watchdog timer receives an indication of a change in a mode of operation in the processing system. In response to the change in the mode of operation of the processing system, the watchdog timer changes the time out period to a second time out period corresponding to the new mode of operation.

Claims (33)

1. A method comprising:

receiving an indication of a change in a mode of operation in a processing system having a time out functionality, wherein the change in the mode of operation comprises at least one of a change in operating frequency of the processing system or a change in power used by the processing system;

changing a first time out period to a second time out period in response to the change in the mode of operation; and

in response to an expiration of the second time out period, providing a signal to the processing system.

2. The method of claim 1 , wherein providing the signal comprises providing at least one of a reset signal or an interrupt request.

3. The method of claim 2 , wherein providing the signal comprises providing the reset signal when the processing system is in a normal mode of operation.

4. The method of claim 2 , wherein providing the signal comprises providing the interrupt request when the processing system is in a low power mode of operation.

5. The method of claim 1 , wherein the processing system comprises at least one watchdog timer to implement the time out functionality.

6. The method of claim 5 , further comprising:

receiving a watchdog timer feed signal; and

changing the first time out period to the second time out period upon receiving the watchdog timer feed signal.

7. The method of claim 6 , wherein the first time out period is different than the second time out period.

8. An apparatus comprising:

a processing system;

a mode controller coupled to the processing system, the mode controller to establish a change in a mode of operation of the processing system, wherein the change in the mode of operation comprises at least one of a change in operating frequency of the processing system or a change in power used by the processing system; and

a time out circuit coupled to the processing system and the mode controller, the time out circuit configured to change a time out period from a first time out period to a second time out period in response to the change in the mode of operation of the processing system, and, in response to an expiration of the second time out period, provide a signal to the processing system.

9. The apparatus of claim 8 , wherein to provide the signal, the time out circuit to provide at least one of a reset signal or an interrupt request, based on the mode of operation of the processing system.

10. The apparatus of claim 9 , wherein to provide the signal, the time out circuit to provide the reset signal when the processing system is in a normal mode of operation.

11. The apparatus of claim 9 , wherein to provide the signal, the time out circuit to provide the interrupt request when the processing system is in a low power mode of operation.

12. The apparatus of claim 8 , wherein the time out circuit comprises at least one watchdog timer to measure the first time out period and the second time out period.

13. The apparatus of claim 12 , wherein the time out circuit comprises a control circuit configured to:

receive a watchdog timer feed signal; and

change the time out period of the watchdog timer circuit upon receiving the watchdog timer feed signal.

14. The apparatus of claim 8 , wherein the first time out period is different than the second time out period.

15. The apparatus of claim 8 , wherein to establish a change in a mode of operation of the processing system, the mode controller to at least one of detect the mode of operation or set the mode of operation.

16. An apparatus comprising:

a processing system having a time out functionality;

a first circuit configured to change a time out period from a first time out period to a second time out period in response to a change in a mode of operation of the processing system, wherein the first time out period is different than the second time out period; and

a second circuit configured to provide a signal to the processing system in response to an expiration of the second time out period, wherein the change in the mode of operation comprises at least one of a change in operating frequency of the processing system or a change in power used by the processing system.

17. The apparatus of claim 16 , wherein the first circuit configured to change the time out period is further configured to operate during active operation of the processing system.

18. The apparatus of claim 16 , wherein to provide the signal, the second circuit to provide at least one of a reset signal or an interrupt request, based on the mode of operation of the processing system.

19. The apparatus of claim 18 , wherein to provide the signal, the second circuit to provide the reset signal when the processing system is in a normal mode of operation.

20. The apparatus of claim 18 , wherein to provide the signal, the second circuit to provide the interrupt request when the processing system is in a low power mode of operation.

Assignments (7)
RELEASE OF SECURITY INTEREST Recorded Mar 16, 2022
From: MUFG UNION BANK, N.A.
To: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
Reel/Frame 059410/0438 →
RELEASE OF SECURITY INTEREST Recorded Sep 14, 2021
From: MUFG UNION BANK, N.A.,
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 057501/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 24, 2020
From: CYPRESS SEMICONDUCTOR CORPORATION
To: MONTEREY RESEARCH, LLC
Reel/Frame 052487/0808 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST Recorded Dec 5, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: MUFG UNION BANK, N.A.
Reel/Frame 051209/0721 →
CORRECTIVE ASSIGNMENT TO CORRECT THE FOLLOWING NUMBERS 6272046,7277824,7282374,7286384,7299106,7337032,7460920,7519447 PREVIOUSLY RECORDED ON REEL 039676 FRAME 0237. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Oct 16, 2018
From: CYPRESS SEMICONDUCTOR CORPORATION
To: MORGAN STANLEY SENIOR FUNDING
Reel/Frame 047797/0854 →
SECURITY INTEREST Recorded Aug 15, 2016
From: CYPRESS SEMICONDUCTOR CORPORATION
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039676/0237 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 2, 2015
From: SHEETS, MICHAEL; WRIGHT, DAVID G.
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 036938/0068 →