Method and system for forward error correction decoding with parity check for use in low complexity highly-spectrally efficient communications
A receiver receives an inter-symbol correlated (ISC) signal with information symbols and a corresponding parity symbol. Values of information symbols are estimated utilizing parity samples that are generated from the parity symbols. One or more maximum likelihood (ML) decoding metrics are generated for the information symbols. One or more estimations are generated for the information symbols based on the one or more ML decoding metrics. A parity metric is generated for each of the one or more generated estimations of the information symbols. The parity metric is generated by summing a plurality of values of one of the generated estimations to generate a sum, and wrapping the sum to obtain a parity check value that is within the boundaries of a symbol constellation utilized in generating the information symbols.
1. A transmitter comprising:
a symbol mapper circuit configured to map a plurality of information bits to a plurality of information symbols of an output symbol stream;
a symbol-domain parity value insertion circuit configured to:
process said plurality of information symbols according to a parity function to generate a parity value; and
add said parity value to said output symbol stream prior to said output symbol stream being transmitted onto a communication channel; and
a transmitter front-end circuit configured to transmit the output symbol stream, after addition of the parity value, onto the communication channel.
2. The transmitter of claim 1 , wherein said parity function is a non-linear function.
3. The transmitter of claim 1 , wherein said parity function is a linear function.
4. The transmitter of claim 1 , wherein said parity function incorporates a modulo operation that ensures that the amplitude of said parity value is with the maximum of the symbol constellation in use by said transmitter.
5. The transmitter of claim 1 , wherein said symbol-domain parity value insertion circuit comprises a pulse shaping filter.
6. The transmitter of claim 5 , wherein a response of said pulse shaping filer is adjusted based on feedback from a receiver of said output symbol stream.
7. The transmitter of claim 6 , wherein said feedback comprises one or both of:
a symbol error rate for said output symbol stream and a bit error rate for said output symbol stream.
8. The transmitter of claim 1 , wherein which symbols of said output symbol stream are processed by said symbol-domain parity value insertion circuit is determined based on feedback from a receiver of said output symbol stream.
9. The transmitter of claim 8 , wherein said feedback comprises a signal-to-noise ratio value for said output symbol stream.
10. The transmitter of claim 8 , wherein said feedback comprises one or both of:
a symbol error rate for said output symbol stream and a bit error rate for said output symbol stream.
11. A method comprising:
mapping, by a symbol mapper circuit of a transmitter, a plurality of information bits to a plurality of information symbols of an output symbol stream;
processing, by a symbol-domain parity value insertion circuit of said transmitter, said plurality of information symbols according to a parity function to generate a parity value;
adding, by said symbol-domain parity value insertion circuit of said transmitter, said parity value to said output symbol stream prior to said output symbol stream being transmitted onto a communication channel; and
transmitting, by a transmitter front-end circuit of the transmitter, the output symbol stream, after addition of the parity value, onto the communication channel.
12. The method of claim 11 , wherein said parity function is a non-linear function.
13. The method of claim 11 , wherein said parity function is a linear function.
14. The method of claim 11 , wherein said parity function incorporates a modulo operation that ensures that the amplitude of said parity value is with the maximum of the symbol constellation in use by said transmitter.
15. The method of claim 11 , wherein said symbol-domain parity value insertion circuit comprises a pulse shaping filter.
16. The method of claim 15 , wherein a response of said pulse shaping filer is adjusted based on feedback from a receiver of said output symbol stream.
17. The method of claim 16 , wherein said feedback comprises one or both of:
a symbol error rate for said output symbol stream and a bit error rate for said output symbol stream.
18. The method of claim 11 , wherein which symbols of said output symbol stream are processed by said symbol-domain parity value insertion circuit is determined based on feedback from a receiver of said output symbol stream.
19. The method of claim 18 , wherein said feedback comprises a signal-to-noise ratio value for said output symbol stream.
20. The method of claim 18 , wherein said feedback comprises one or both of:
a symbol error rate for said output symbol stream and a bit error rate for said output symbol stream.