System and method of interfacing co-processors and input/output devices via a main memory system
View Patent ↗A system for interfacing with a co-processor or input/output device is disclosed. According to one embodiment, the system includes a computer processing unit, a memory module, a memory bus that connects the computer processing unit and the memory module, and a co-processing unit or input/output device, wherein the memory bus also connects the co-processing unit or input/output device to the computer processing unit.
1. A device comprising:
a processing unit;
an I/O interface configured to communicate with a co-processing unit or input/output device;
a host interface configured to communicate with a host memory controller of a host system over a memory bus; and
a data de-interleaver configured to:
determine an interleaving mapping of the host memory controller; and
generate de-interleaved data from bit-interleaved data received from the host memory controller.
2. The device of claim 1 further comprises an ASIC that processes address and data bus signals received from and sent to the memory bus.
3. The device of claim 1 further comprising a memory interface configured to communicate with one or more ranks of memory devices.
4. The device of claim 2 further comprising a software driver that communicates commands to the ASIC.
5. The device of claim 2 , wherein the device detects and initializes the ASIC, after a BIOS memory test operation is performed and prior to booting an operating system the host system.
6. The device of claim 5 , wherein initializing the ASIC includes learning an error-code detection (ECC) that the processing unit uses by solving for a generator vector associated with each data bus signal.
7. The device of claim 5 , wherein initializing the ASIC includes loading ECC, configuration parameters from at least one of a serial ROM and a system management bus (SMBus), and wherein the ECC configuration parameters are used by the processing unit to solve for a generator vector associated with each data bus signal.
8. The device of claim 2 , wherein the address and data bus signals includes generating ECC value based on an associated data value.
9. The device of claim 1 , wherein the co-processing unit or input/output device includes an encryption unit.
10. The device of claim 1 , wherein the co-processing unit or input/output device includes a compression unit.
11. The device of claim 1 , wherein the co-processing unit or input/output device includes a digital signal processing unit.
12. The device of claim 1 , wherein the co-processing unit or input/output device includes an image processing unit.
13. The device of claim 1 , wherein the co-processing unit or input/output device includes a pattern matching unit.
14. The device of claim 1 , wherein the co-processing unit or input/output device includes a wireless communications unit.
15. The device of claim 1 , wherein the co-processing unit or input/output device includes a redundant array of independent disks (RAID) control unit.
16. A device comprising:
a processing unit;
an I/O interface configured to communicate with a co-processing unit or input/output device;
a host interface configured to communicate a host memory controller of a host system over a memory bus; and
a data descramble configured to:
determine a scrambler sequence; and
generate descrambled data by descrambling bit-interleaved data received from the host memory controller, wherein the bi-interleaved data is scrambled based on an address associated with the bit-interleaved data and the scramble sequence.
17. The device of claim 16 , wherein the data descrambler is configured to descramble a data value received from the host system and scrambling a value for sending to the host system, the unscrambling and scrambling is performed based on associated address values.
18. The device of claim 16 , wherein the scramble sequence is determined by solving for a generator vector associated with each address bus signal.
19. A device comprising:
a processing unit;
an I/O interface configured to communicate a co-processing unit or input/output device;
a host interface configured to communicate with a host memory controller of a host system over a memory bus; and
a data de-interleaver configured to:
identify information of an interleaving pattern of the host memory controller;
determine that the interleaving pattern of the host memory controller is known; and
generate de-interleaved data from bit-interleaved data received from the host memory controller based on the information of the interleaving pattern.
20. The device of claim 19 , wherein the data de-interleaver is further configured to:
store the information of the interleaving pattern of the host memory controller in a non-volatile storage; and
read the information of the interleaving pattern from the non-volatile storage.
21. The device of claim 19 , wherein the information of the interleaving pattern of the host memory controller is stored in a configuration register.
22. The device of claim 19 , wherein the data de-interleaver is further configured to load the information of the interleaving pattern of the host memory controller from an external device via a SMBus.
23. The device of claim 22 , wherein the information of the interleaving pattern of the host memory controller is loaded from BIOS, a discovery boot loader, or a device driver.
24. The device of claim 19 , wherein the data de-interleaver is further configured to bypass learning of the interleaving pattern of the host memory controller.
25. A device comprising:
a processing unit;
an I/O interface configured to communicate with a co-processing unit or input/output device;
a host interface configured to communicate with a host memory controller of a host system over a memory bus; and
an ECC generator configured to:
identify information of an ECC generation pattern of the host memory controller:
determine that the ECC generation pattern of the host memory controller is known; and
generate ECC data from data received from the host memory controller based on the information of the ECC generation pattern.
26. The device of claim 25 , wherein the ECC generator is further configured to:
store the information of the ECC generation pattern of the host memory controller in a non-volatile storage; and
read the information of the ECC generation pattern from the non-volatile storage.
27. The device of claim 25 , wherein the information of the ECC generation pattern of the host memory controller is stored in a configuration register.
28. The device of claim 25 , wherein the ECC generator is further configured to load the information of the ECC generation pattern of the host memory controller from an external device via a SMBus.
29. The device of claim 28 , wherein the information of the ECC generation pattern of the host memory controller is loaded from BIOS, a discovery boot loader, or a device driver.
30. The device of claim 25 , wherein the ECC generator is further configured to bypass learning of the ECC generation pattern of the host memory controller.
31. A device comprising:
a processing unit;
an I/O interface configured to communicate with a co-processing unit or input/output device;
a host interface configured to communicate a host memory controller of a host system over a memory bus; and
a data descrambler configured to:
identify information of a scrambler sequence of the host memory controller;
determine at the scrambler sequence of the host memory controller is known; and
generate descrambled data from scrambled data received from the host memory controller based on the information of the scrambler sequence.
32. The device of claim 31 , wherein the data descrambler is further configured to:
store the information of the scrambler sequence of the host memory controller in a non-volatile storage; and
read the information of the scrambler sequence from the non-volatile storage.
33. The device of claim 31 , wherein the information of the scrambler sequence of the host memory controller is stored in a configuration register.
34. The device of claim 31 , wherein the data descrambler is further configured to load the information of the scrambler sequence of the host memory controller from an external device via a SMBus.
35. The device of claim 34 , wherein the information of the scrambler sequence of the host memory controller is loaded from BIOS, a discovery boot loader, or a device driver.
36. The device of claim 31 , wherein the data descrambler is further configured to bypass learning of the scrambler sequence of the host memory controller.
37. The device of claim 16 , wherein the data descrambler is further configured to:
determine a scramble vector for each address bit of an n-bit address space associated with the device, and
apply one or more of the scramble vectors to descramble the bit-interleaved data based on an address associated with the bit-interleaved data.