Load aware voltage regulator and dynamic voltage and frequency scaling
A voltage regulator and/or associated circuitry provides an indication of average current consumed or drawn by a load, level and magnitude of transient events, and regulation efficiency. A dynamic voltage and frequency scaling governor makes use of the indication of average current consumed or drawn by the load, level and magnitude of transient events, and regulation efficiency to help optimize operation of the load, with respect to power and/or performance.
1. A system useful in provision of power to integrated circuitry forming a load, comprising:
a voltage regulator configured to receive power from a power source and provide regulated power to a load in accordance with a requested voltage level, the voltage regulator including circuitry for determining a signal indicative of average current supplied by the voltage regulator;
an automatic transient control (ATC) circuit connected to the load in parallel with the voltage regulator, and the ATC circuit providing a plurality of paths between the power source and the load, the ATC circuit configured to provide power to the load for short periods so as to increase power provided to the load, the ATC circuit including circuitry for providing a signal indicative of a number of ATC activations;
a dynamic voltage and frequency scaling (DVFS) governor configured to determine the requested voltage level to be applied to the load and a frequency of a clock signal to be used by circuitry of the load, the DVFS governor configured to adjust at least one of the requested voltage level to be applied to the load and the frequency of the clock signal to be used by circuitry of the load based on the signal indicative of the number of ATC activations.
2. The system of claim 1 , wherein the ATC circuit further includes circuitry for providing a signal indicative of average magnitude of ATC activations.
3. The system of claim 2 , wherein the DVFS governor is configured to reduce the frequency of the clock signal to be used by circuitry of the load when the average magnitude of ATC activations exceeds a predefined magnitude.
4. The system of claim 2 , wherein the DVFS governor is configured to reduce the requested voltage to be applied to the load when the average magnitude of ATC activations exceeds a predefined magnitude.
5. The system of claim 2 , wherein the DVFS governor is configured to reduce the average magnitude of ATC activations based on the signal indicative of average magnitude of ATC activations.
6. The system of claim 2 , wherein the DVFS governor is configured to reduce the frequency of the clock signal to be used by circuitry of the load, the reduction of the frequency of the clock signal is for reducing the average magnitude of ATC activations.
7. The system of claim 2 , wherein the DVFS governor is configured to reduce the voltage to be applied to the load, the reduction of the voltage to be applied to the load is for reducing the average magnitude of ATC activations.
8. The system of claim 1 , wherein the DVFS governor is configured to reduce the frequency of the clock signal to be used by circuitry of the load when the number of ATC activations exceeds a predefined value.
9. The system of claim 1 , wherein the DVFS governor is configured to reduce the voltage to be applied to the load when the number of ATC activations exceeds a predefined value.
10. The system of claim 1 , wherein the DVFS governor is configured to reduce the number of ATC activations based on the signal indicative of number of ATC activations.
11. The system of claim 1 , wherein the DVFS governor is configured to reduce the frequency of the clock signal to be used by circuitry of the load, the reduction of the frequency of the clock signal is for reducing the number of ATC activations.
12. The system of claim 1 , wherein the DVFS governor is configured to reduce the voltage to be applied to the load, the reduction of the voltage to be applied to the load is for reducing the number of ATC activations.
13. The system of claim 1 , wherein the DVFS governor is further configured to provide a signal indicative of a current ramp rate target to the voltage regulator.
14. The system of claim 13 , wherein the voltage regulator is configured to command disablement of the ATC circuit based on the signal indicative of the current ramp rate target.
15. The system of claim 13 , wherein the voltage regulator is configured to command disablement of the ATC circuit when the current ramp rate target is below a predetermined value.