IP Library Granted Patent US 9,437,498
Granted Patent B2
US 9,437,498 · App. 14/636,778 · Granted Sep 6, 2016

Method for the formation of different gate metal regions of MOS transistors

Inventors: Stéphane Zoll (Froges, FR); Philippe Garnier (Meylan, FR); Olivier Gourhant (Goncelin, FR); Vincent Joseph (Grenoble, FR)
Assignee: STMICROELECTRONICS (CROLLES 2) SAS
H01L21/823437H01L21/0332H01L21/28088H01L21/324H01L29/4966
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Quick Facts
Patent No.
US 9,437,498
App. No.
14/636,778
Granted
Sep 6, 2016
Kind
B2
Abstract

A method is for forming at least two different gates metal regions of at least two MOS transistors. The method may include forming a metal layer on a gate dielectric layer; and forming a metal hard mask on the metal layer, with the hard mask having a composition different from that of the metal layer and covering a first region of the metal layer and leaving open a second region of the metal layer. The method may also include diffusion annealing the intermediate structure obtained in the prior steps such as to make the metal atoms of the hard mask diffuse into the first region, and removal of the hard mask.

Claims (26)

1. A method for forming at least two different gate metal regions of at least two MOS transistors comprising:

forming a metal layer with first and second regions on a gate dielectric layer;

forming a metal hard mask on the metal layer, the metal hard mask having a composition different from that of the metal layer, and covering the first region of the metal layer to define an intermediate structure and leaving open the second region of the metal layer;

diffusion annealing the intermediate structure to make metal atoms of the metal hard mask diffuse into the first region of the metal layer, with the diffusion annealing being carried out in presence of a gaseous mixture comprising ammonia for nitriding the second region of the metal layer so as to increase a nitrogen concentration thereof; and

removing the metal hard mask.

2. The method according to claim 1 , wherein diffusion annealing comprises rapid thermal annealing.

3. The method according to claim 2 , wherein the rapid thermal annealing is carried out for a duration in a range between 1 second and 5 minutes.

4. The method according to claim 2 , wherein the rapid thermal annealing is carried out in a temperature range between 400° C. and 1200° C.

5. The method according to claim 1 , wherein the metal layer comprises titanium nitride.

6. The method according to claim 1 , wherein the metal hard mask comprises a metal selected from the group consisting of aluminum, chrome, manganese, molybdenum, tungsten, tantalum, rhenium, ruthenium, cobalt, nickel, lanthanum, or an oxide of a metal from the group or a nitride of a metal from the group.

7. A method for making an integrated circuit including at least two different gate metal regions of at least two MOS transistors, the method comprising:

forming a metal layer with first and second regions on a gate dielectric layer above a substrate;

forming a metal hard mask on the metal layer, the metal hard mask having a composition different from that of the metal layer, and covering the first region of the metal layer to define an intermediate structure and leaving open the second region of the metal layer;

rapid thermal annealing the intermediate structure to make metal atoms of the metal hard mask diffuse into the first region of the metal layer, with the rapid thermal annealing being carried out in presence of a gaseous mixture comprising ammonia for nitriding the second region of the metal layer so as to increase a nitrogen concentration thereof; and

removing the metal hard mask.

8. The method according to claim 7 , wherein the rapid thermal annealing is carried out for a duration in a range between 1 second and 5 minutes in a temperature range between 400° C. and 1200° C.

9. The method according to claim 7 , wherein the metal layer comprises titanium nitride.

10. The method according to claim 7 , wherein the metal hard mask comprises a metal selected from the group consisting of aluminum, chrome, manganese, molybdenum, tungsten, tantalum, rhenium, ruthenium, cobalt, nickel, lanthanum, or an oxide of a metal from the group or a nitride of a metal from the group.

11. A method for making an integrated circuit including at least two different gate metal regions of at least two MOS transistors, the method comprising:

forming a metal layer with first and second regions on a gate dielectric layer;

forming a hard mask on the metal layer, the hard mask having a composition different from that of the metal layer, and covering the first region of the metal layer and leaving open the second region of the metal layer; and

diffusing atoms of the hard mask into the first region of the metal layer, with the diffusion being carried out in presence of a gaseous mixture comprising ammonia for nitriding the second region of the metal layer so as to increase a nitrogen concentration thereof.

12. The method according to claim 11 , wherein diffusing comprises performing a rapid thermal annealing.

13. The method according to claim 12 , wherein the rapid thermal annealing is carried out for a duration in a range between 1 second and 5 minutes in a temperature range between 400° C. and 1200° C.

14. The method according to claim 11 , wherein the metal layer comprises titanium nitride.

15. The method according to claim 11 , wherein the metal hard mask comprises a metal selected from the group consisting of aluminum, chrome, manganese, molybdenum, tungsten, tantalum, rhenium, ruthenium, cobalt, nickel, lanthanum, or an oxide of a metal from the group or a nitride of a metal from the group.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 10, 2023
From: STMICROELECTRONICS (CROLLES 2) SAS
To: STMICROELECTRONICS INTERNATIONAL N.V.
Reel/Frame 063276/0569 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 5, 2015
From: ZOLL, STEPHANE; GARNIER, PHILIPPE; GOURHANT, OLIVIER; JOSEPH, VINCENT
To: STMICROELECTRONICS (CROLLES 2) SAS
Reel/Frame 035092/0936 →
Priority Claims (1)
FR 14 52130 · Mar 14, 2014 · national
Continuity (1)
Related Publication 20150262884A1 · Sep 17, 2015