Apparatus and method for detecting single flip-error in a complementary resistive memory
Described is an apparatus which comprises: a complementary resistive memory bit-cell; a first sense amplifier coupled to the complementary resistive memory bit-cell via access devices; a second sense amplifier coupled to the first sense amplifier and to the complementary resistive memory bit-cell via the access devices, wherein the second sense amplifier is operable to detect an error in the complementary resistive memory bit-cell.
1. An apparatus comprising:
a complementary resistive memory bit-cell;
a first sense amplifier coupled to the complementary resistive memory bit-cell via access devices; and
a second sense amplifier coupled to the first sense amplifier and to the complementary resistive memory bit-cell via the access devices, wherein the second sense amplifier is operable to detect an error in the complementary resistive memory bit-cell.
2. The apparatus of claim 1 , wherein the second sense amplifier is operable to output a pre-determined value when any of the memory bit-cells in the complementary resistive memory bit-cell flips.
3. The apparatus of claim 2 comprises a detector coupled to the second sense amplifier, the detector to process the output of the second sense amplifier, and wherein an output of the detector indicates a location of an error in a memory array having the complementary resistive memory bit-cell.
4. The apparatus of claim 3 comprises a correction logic to apply errors-and-erasures decoding.
5. The apparatus of claim 3 , wherein the detector is an exclusive-NOR (XNOR) logic gate.
6. The apparatus of claim 3 , wherein the memory is at least one of:
a magnetic random access memory (MRAM); or
a Phase Change Memory (PCM).
7. The apparatus of claim 1 , wherein the second amplifier comprises:
a first p-type transistor coupled to a power supply and controllable by a control signal; and
a second p-type transistor coupled to the power supply and controllable by the control signal.
8. The apparatus of claim 7 , wherein the second amplifier comprises:
a third p-type transistor coupled in series with the first p-type transistor, and wherein the third p-type transistor has a gate terminal coupled to one of the access devices that further couples to a bit-line.
9. The apparatus of claim 8 , wherein the second amplifier comprises:
a fourth p-type transistor coupled in series with the second p-type transistor, and wherein the fourth p-type transistor has a gate terminal coupled to one of the access devices that further couples to a complementary bit-line.
10. The apparatus of claim 9 , wherein the second amplifier comprises:
a first n-type transistor coupled in series with the third p-type transistor and to ground and controllable by the control signal; and
a second n-type transistor coupled in series with the fourth p-type transistor and to the ground and controllable by the control signal.
11. The apparatus of claim 1 , wherein the complementary resistive memory bit-cell comprises at least one of:
a magnetic tunneling junction (MTJ) device;
a phase change memory (PCM) cell; or
a resistive random access memory (ReRAM) cell.
12. A system comprising:
a processor;
a memory coupled to the processor, the memory including:
an array of complementary resistive memory bit-cells;
a first sense amplifier coupled to at least one of the complementary resistive memory bit-cells of the array via access devices; and
a second sense amplifier coupled to the first sense amplifier and to the at least one of the complementary resistive memory bit-cells via the access devices, wherein the second sense amplifier is operable to output a pre-determined value when any of the memory bit-cells in the at least one complementary resistive memory bit-cell flips; and
a wireless interface for allowing the processor to communicate with another device.
13. The system of claim 12 , wherein the processor and the memory are integrated in a three dimensional stacked integrated circuit.
14. The system of claim 12 , wherein the processor comprises a correction logic to apply an errors-and-erasures decoding.
15. The system of claim 12 , wherein the memory comprises a detector coupled to the second sense amplifier, wherein the detector to process the output of the second sense amplifier, and wherein an output of the detector indicates a location of an error in the array.
16. The system of claim 15 , wherein the detector is an exclusive-NOR (XNOR) logic gate.
17. The system of claim 12 , wherein the memory is at least one of:
a magnetic random access memory (MRAM); or
a Phase Change Memory (PCM).
18. The system of claim 12 , wherein the complementary resistive memory bit-cell comprises at least one of:
a magnetic tunneling junction (MTJ) device;
a phase change memory (PCM) cell; or
a resistive random access memory (ReRAM) cell.
19. A method comprising:
reading an array of complementary resistive memory bit-cells;
providing an output of a first sense amplifier which is coupled to the array via access devices;
providing an output of a second sense amplifier which is coupled to the first sense amplifier and to the array via the access devices; and
identifying a location of error by processing the output generated by the second amplifier.
20. The method of claim 19 comprises:
performing errors-and-erasures decoding, on the output generated by the first sense amplifier, by applying the identified location of the error in the array.