Compact low-power fully digital CMOS clock generation apparatus for high-speed SerDes
View Patent ↗A high-speed clock generator device includes a phase-interpolator (PI) circuit, a smoothing block, and inverter-based low-pass filters. The PI circuit receives a multiple clock signals with different phase angles and generates an output clock signal having a correct phase angle. The smoothing block smooths the clock signals with different phase angles and generates a number of smooth clock signals featuring improved linearity. The inverter-based low-pass filters filter harmonics of the clock signals with different phase angles.
1. A high-speed clock generator device, the device comprising:
a phase-interpolator (PI) circuit configured to receive a plurality of clock signals with different phase angles and to generate an output clock signal having a correct phase angle;
a smoothing block configured to smooth the plurality of clock signals with different phase angles and to generate a plurality of smooth clock signals featuring improved linearity; and
inverter-based low-pass filters configured to filter harmonics of the plurality of clock signals with different phase angles.
2. The device of claim 1 , wherein the device further comprises an injection locking-ring oscillator (ILRO) configured to receive one or more input clock signals and to generate the plurality of clock signals with different phase angles, and wherein the ILRO comprises a compact and low power wide-band ILRO, and wherein the ILRO comprises a strong injection ILRO with a current-limited delay line implemented in CMOS.
3. The device of claim 2 , wherein the ILRO is configured to reduce an impact on device noise as compared to delay line loop (DLL) implementation with large loop filter, and wherein an injection strength and a tracking bandwidth of the ILRO are configured to be programmable.
4. The device of claim 2 , wherein the ILRO is configured to receive the one or more input clock signals from a phase-locked loop (PLL), and wherein the ILRO is configured to generate full-rate multi-phase clock signals.
5. The device of claim 4 , wherein the full-rate multi-phase clock signals comprises:
four in-phase (I) and quadrature-phase (Q) clock signals at a full rate, and
16-phase clock signals at a reduced rate that is one-fourth of a full rate.
6. The device of claim 4 , wherein the ILRO is configured to generate the full-rate multi-phase clock signals while maintaining a same resolution and number of PI-codes and providing a linear power scaling with frequency and an improved linearity response.
7. The device of claim 1 , wherein the device comprises a scalable multi-rate device, wherein the device comprises a digital device implemented in CMOS, and wherein the PI circuit comprises a programmable digital PI.
8. The device of claim 1 , further comprising a pulling block comprising tri-state crossed-coupled inverters configured to improve linearity by pulling edges of the plurality of smooth clock signals closer to one another.
9. A method for high-speed clock generation, the method comprising:
receiving a plurality of clock signals with different phase angles; and
generating an output clock signal having a correct phase angle based on the plurality of clock signals with different phase angles by using inverter-based low-pass filters to perform smoothing of the plurality of clock signals with different phase angles, wherein the generated plurality of smooth clock signals feature improved linearity.
10. The method of claim 9 , wherein the high-speed clock generation is performed by using a scalable multi-rate digital device implemented in CMOS, and wherein the plurality of clock signals with different phase angles are received from an injection locking-ring oscillator (ILRO).
11. The method of claim 10 , further comprising receiving at the one or more input clock signals, and wherein the ILRO comprises a compact, low power, strong injection, and wide-band ILRO with a current-limited delay line implemented in CMOS.
12. The method of claim 11 , further comprising:
configuring the ILRO to reduce an impact on device noise as compared to delay line loop (DLL) implementation with large loop filter, and
programming an injection strength and a tracking bandwidth of the ILRO.
13. The method of claim 11 , further comprising configuring the ILRO to:
receive the one or more input clock signals from a phase-locked loop (PLL); and
generate the full-rate multi-phase clock signals based on the one or more input clock signals.
14. The method of claim 13 , wherein the full-rate multi-phase clock signals comprise four in-phase (I) and quadrature-phase (Q) clock signals at a full rate, and 16-phase clock signals at a reduced rate that is one-fourth of a full rate.
15. The method of claim 13 , wherein generating the full-rate multi-phase clock signals comprises maintaining a same resolution and number of PI-codes and maintaining an improved linearity response and a linear power scaling with frequency.
16. The method of claim 9 , wherein:
generating an output clock signal having the correct phase angle comprises using a phase interpolator (PI) comprising a programmable digital PI, and
the method comprises configuring the inverter-based low-pass filters to filter harmonics of the plurality of clock signals with different phase angles to improve the linearity.
17. The method of claim 9 , comprising pulling edges of the plurality of smooth clock signals by using a pulling block comprising tri-state crossed-coupled inverters configured to improve linearity by pulling edges of the plurality of smooth clock signals closer to one another.
18. A high-speed digital system for communication between two endpoints, the system comprising:
a receive path configured to receive, at a first endpoint, a serial digital signal, to correct a phase of the serial digital signal using a digital device, and to generate a parallel digital signal for processing in a digital signal processor (DSP); and
a transmit path configured to receive an output of the DSP and to generate a serial digital signal for transmission to a second endpoint,
wherein the digital device comprises:
a phase-interpolator (PI) circuit configured to receive a plurality of clock signals with different phase angles and to generate an output clock signal having a correct phase angle, the PI circuit comprising a smoothing block comprising inverter-based low-pass filters configured to filter harmonics of the plurality of clock signals with different phase angles and to smooth the plurality of clock signals with different phase angles to generate a plurality of smooth clock signals with improved linearity.
19. The system of claim 18 , wherein:
the digital device further comprises an injection locking-ring oscillator (ILRO) configured to receive one or more input clock signals and to generate the plurality of clock signals with different phase angles,
the ILRO is configured to receive the one or more input clock signals from a phase-locked loop (PLL) and to generate full-rate multi-phase clock signals, and
the PI circuit comprises:
a programmable digital PI, and
a pulling block comprising a tri-state crossed-coupled inverters configured to improve linearity by pulling edges of the plurality of smooth clock signals closer to one another.
20. A phase interpolator (PI) circuit, the circuit comprising:
a smoothing block configured to smooth a plurality of clock signals; and
inverter-based low-pass filters configured to filter harmonics of the plurality of clock signals with different phase angles,
wherein:
the plurality of clock signals comprise clock signals with different phase angles,
the smoothing block is configured to smooth the plurality of clock signals with different phase angles to generate a plurality of smooth clock signals with improved linearity, and
an output clock signal generated by the PI circuit has a correct phase angle.