Compact semiconductor memory device having reduced number of contacts, methods of operating and methods of making
An integrated circuit including a link or string of semiconductor memory cells, wherein each memory cell includes a floating body region for storing data. The link or string includes at least one contact configured to electrically connect the memory cells to at least one control line, and the number of contacts in the string or link is the same as or less than the number of memory cells in the string or link.
1. An integrated circuit comprising:
a link or string of semiconductor memory cells, wherein each said memory cell comprises:
a floating body region for storing data indicating a state of said memory cell; and
a back-bias region configured to inject charge into said floating body region to maintain said state of said memory cell;
wherein an amount of charge injected into said floating body is a function of a charge stored in said floating body region;
wherein said link or string comprises at least one contact configured to electrically connect said memory cells to at least one control line; and
wherein a number of said at least one contact is the same as or less than a number of said memory cells in said link or string.
2. The integrated circuit of claim 1 , wherein said number of said at least one contact is less than said number of memory cells.
3. The integrated circuit of claim 1 , where said semiconductor memory cells are connected in series.
4. The integrated circuit of claim 1 , where said semiconductor memory cells are connected in parallel.
5. The integrated circuit of claim 1 , where said integrated circuit is fabricated on a bulk silicon substrate.
6. The integrated circuit of claim 1 , where said number of said at least one contact is two.
7. The integrated circuit of claim 1 , wherein said memory cells further comprise first and second conductive regions interfacing with said floating body region.
8. The integrated circuit of claim 1 , wherein each said memory cell further comprises a gate insulated from said floating body region.
9. The integrated circuit of claim 1 , wherein at least one of said memory cells is a contactless memory cell.
10. The integrated circuit of claim 9 , wherein a majority of said memory cells are contactless memory cells.
11. An integrated circuit comprising:
a link or string of semiconductor memory cells, wherein each said memory cell comprises a floating body region for storing data;
wherein said link or string comprises at least one contact configured to electrically connect said memory cells to at least one control line;
wherein a number of said at least one contact is the same as or less than a number of said memory cells in said link or string; and
wherein said at least one control line is connected to a read circuitry.
12. The integrated circuit of claim 11 , wherein said number of said at least one contact is less than said number of said memory cells.
13. The integrated circuit of claim 11 , where said semiconductor memory cells are connected in series.
14. The integrated circuit of claim 11 , where said semiconductor memory cells are connected in parallel.
15. The integrated circuit of claim 11 , where said integrated circuit is fabricated on a bulk silicon substrate.
16. The integrated circuit of claim 11 , where said number of said at least one contact is two.
17. The integrated circuit of claim 11 , wherein said memory cells further comprise first and second conductive regions interfacing with said floating body region.
18. The integrated circuit of claim 11 , wherein each said memory cell further comprises a gate insulated from said floating body region.
19. The integrated circuit of claim 11 , wherein at least one of said memory cells is a contactless memory cell.
20. The integrated circuit of claim 19 , wherein a majority of said memory cells are contactless memory cells.