Long-distance high-speed data and clock transmission
View Patent ↗A non-linear impedance terminates a transmission line. The non-linear impedance may be implemented with a back-to-back connected inverter pair. The pair acts as a non-linear resistor. A process, voltage, temperature (PVT) tracking circuit may also be provided to improve PVT tracking, with resistance of transistors locked to a calibrated resistor. The replica circuit does not appear in the signal path, and does not add capacitive load.
1. A transmission line comprising:
a signal path comprising:
a signal propagation medium; and
a termination point along the signal propagation medium; and
a non-linear impedance connected at the termination point along the signal path, wherein the non-linear impedance comprises a first inverter and a second inverter, wherein a first gate of a positive side transistor in the first inverter is connected to a second gate of a positive side transistor in the second inverter, and a third gate of a negative side transistor in the first inverter is connected to a fourth gate of a negative side transistor in the second inverter, wherein the non-linear impedance is configured to:
present a negative impedance in response to a first range of input voltage, wherein the first range of input voltage is below a power supply input voltage applied to the non-linear impedance; and
present a positive impedance in response to a second range of input voltage, wherein the second range of input voltage is above the power supply input voltage.
2. The transmission line of claim 1 , where:
the non-linear impedance comprises a non-linear resistor.
3. The transmission line of claim 1 , further comprising:
a bias circuit comprising:
a reference voltage input configured to be one-half of the input voltage; and
a calibrated output impedance connected to the non-linear impedance.
4. The transmission line of claim 1 , where:
the non-linear impedance is voltage controlled.
5. The transmission line of claim 1 , where:
the signal path comprises a differential signal path.
6. The transmission line of claim 5 , where:
the differential signal path comprises a first path and a second path;
the input voltage comprises a differential voltage comprising a positive component and a negative component;
the non-linear impedance comprises:
the first inverter with a first input configured to receive the positive component of the differential voltage;
the second inverter with a second input configured to receive the negative component of the differential voltage; and where:
the first inverter is connected back-to-back with the second inverter;
the first input is connected to the first path; and
the second input is connected to the second path.
7. The transmission line of claim 5 , where:
the non-linear impedance is connected across the differential signal path.
8. The bias circuit of claim 3 , where:
the reference voltage input comprises a positive side reference voltage;
the calibrated output impedance comprises a positive side calibrated output impedance and a negative side calibrated output impedance; and
the bias circuit is connected to the positive side transistor in the first inverter.
9. The transmission line of claim 1 , where:
the positive transistor in the first inverter is connected to the positive transistor in the second inverter and a positive side bias circuit; and
the negative transistor in the second inverter is connected to the negative transistor in the second inverter and a negative side bias circuit.
10. A transmission line comprising:
a signal path comprising:
a signal propagation medium; and
a termination point along the signal propagation medium;
a non-linear impedance connected at the termination point along the signal path, wherein the non-linear impedance comprises a first inverter and a second inverter, wherein the non-linear impedance is configured to:
present a negative impedance in response to a first range of input voltage, wherein the first range of input voltage is below a power supply input voltage applied to the non-linear impedance; and
present a positive impedance in response to a second range of input voltage, wherein the second range of input voltage is above the power supply input voltage; and
a bias circuit comprising a reference voltage comprising a negative side reference voltage
wherein the bias circuit is connected to a negative side transistor in the first inverter.
11. A method comprising:
identifying a signal path in a circuit layout for which to control signal reflections, the signal path comprising a signal propagation medium;
identifying a termination point along the signal propagation medium; and
in the circuit layout, placing a non-linear impedance at the termination point along the signal path by placing a first inverter connected back-to-back with a second inverter, wherein a first gate of a positive side transistor in the first inverter is connected to a second gate of a positive side transistor in the second inverter, and a third gate of a negative side transistor in the first inverter is connected to a fourth gate of a negative side transistor in the second inverter;
presenting the non-linear impedance as a negative impedance in response to a first range of input voltage, wherein the first range of input voltage is below a power supply input voltage applied to the non-linear impedance; and
presenting the non-linear impedance as a positive impedance in response to a second range of input voltage, wherein the second range of input voltage is above the power supply input voltage.
12. The method of claim 11 , further comprising:
in the circuit layout, placing a bias circuit comprising a reference voltage input and a calibrated output impedance connected to the non-linear impedance.
13. The method of claim 11 , further comprising:
in the circuit layout, placing a positive side bias circuit comprising a positive side reference voltage input and a positive side calibrated output impedance connected to the non-linear impedance; and
in the circuit layout, placing a negative side bias circuit comprising a negative side reference voltage input and a negative side calibrated output impedance connected to the non-linear impedance.
14. The method of claim 11 , where:
placing the non-linear impedance comprises placing a non-linear resistor.
15. The method of claim 14 , where:
the non-linear resistor is a voltage controlled resistor.
16. A circuit comprising:
a first circuit module;
a second circuit module;
a differential signal line connecting the first circuit module and the second circuit module; and
a non-linear impedance connected across the differential signal line, wherein the non-linear impedance comprises a first inverter and a second inverter, wherein a first gate of a positive side transistor in the first inverter is connected to a second gate of a positive side transistor in the second inverter, and a third gate of a negative side transistor in the first inverter is connected to a fourth gate of a negative side transistor in the second inverter, the non-linear impedance configured to:
present a negative impedance in response to a first range of input voltage, wherein the first range of input voltage is below a power supply input voltage applied to the non-linear impedance; and
present a positive impedance in response to a second range of input voltage, wherein the second range of input voltage is above the power supply input voltage.
17. The circuit of claim 16 , where the non-linear impedance comprises a non-linear resistor.
18. The circuit of claim 17 , wherein the non-linear resistor is voltage controlled.
19. The circuit of claim 16 , further comprising a bias circuit module comprising:
a reference voltage input; and
a calibrated output impedance connected to the non-linear impedance.
20. The circuit of claim 16 , where:
the first circuit module and second circuit module are carried in a multiple-chip module package; and
the first inverter is connected back-to-back with the second inverter.