IP Library Granted Patent US 9,374,586
Granted Patent B2
US 9,374,586 · App. 14/639,762 · Granted Jun 21, 2016

Video information processing system with selective chroma deblock filtering

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Quick Facts
Patent No.
US 9,374,586
App. No.
14/639,762
Granted
Jun 21, 2016
Kind
B2
Abstract

A video information processing system including a processing circuit and a deblocking filter. The processing circuit provides video information including a chroma component and a luma component. The deblocking filter has an input receiving the video information and an output providing filtered video information, and is configured to selectively disable chroma deblock filtering while luma deblock filtering is enabled. The processing circuit may include a video encoder or a video decoder. The processing circuit may further include control logic providing a control signal to disable chroma deblock filtering within either or both the encoder and decoder. The video encoder may incorporate control information in the output bitstream to control deblock filtering in the downstream decoder to maintain consistency between the encoder and the decoder.

Claims (51)

1. A deblocking filter for deblock filtering video information which includes luma information and chroma information, said deblocking filter comprising:

a luma deblocking filter which deblock filters said luma information;

a chroma deblocking filter which deblock filters said chroma information; and

control logic which is configured to disable said chroma deblocking filter for at least one macroblock of said video information while said luma deblocking filter is enabled for said at least one macroblock of said video information.

2. The deblocking filter of claim 1 , further comprising:

a memory for storing said luma information and said chroma information; and

wherein said control logic comprises at least one switching device which selectively decouples said chroma deblocking filter from said memory.

3. The deblocking filter of claim 1 , wherein said chroma deblocking filter includes an enable input, wherein said control logic provides an enable signal to said enable input of said chroma deblocking filter.

4. The deblocking filter of claim 1 , further comprising:

a boundary strength circuit that receives said luma information and that provides a boundary strength signal; and

said chroma deblocking filter having a strength select input receiving said strength signal.

5. The deblocking filter of claim 1 , wherein said chroma deblocking filter comprises a blue luma difference deblocking filter and a red luma difference deblocking filter, and wherein said control logic is configured to enable and disable said blue and red luma difference deblocking filters.

6. The deblocking filter of claim 1 , further comprising:

a memory for storing said video information; and

a processor, coupled to said memory, wherein said processor is configured to implement said luma deblocking filter, said chroma deblocking filter and said control logic and to selectively disable chroma deblock filtering.

7. The deblocking filter of claim 6 , wherein said processor controls storing of said video information into said memory, and wherein said processor selectively bypasses storage of said chroma information in said memory when chroma deblock filtering is disabled.

8. A video information processing system, comprising:

a processing circuit for providing video information including a chroma component and a luma component; and

a deblocking filter having an input receiving said video information and an output providing filtered video information, wherein said deblocking filter is configured to disable chroma deblock filtering for at least one macroblock of said video information while luma deblock filtering is enabled for said at least one macroblock of said video information.

9. The video information processing system of claim 8 , wherein said processing circuit comprises:

a video encoder which provides said video information as reconstructed video information; and

control logic which provides a filter control signal to said deblocking filter to disable chroma deblock filtering and enable luma deblock filtering while processing said reconstructed video information.

10. The video information processing system of claim 9 , wherein said video encoder generates residual information, converts said residual information into said reconstructed video information, encodes said residual information into encoded information within an encoded bitstream, and incorporates control information in said encoded bitstream associated with said encoded information, and wherein said control information indicates disabling chroma deblock filtering and enabling luma deblock filtering.

11. The video information processing system of claim 8 , wherein said processing circuit comprises:

a video decoder which provides said video information as decoded reconstructed video information; and

control logic which provides a filter control signal to said deblocking filter to disable chroma deblock filtering and enable luma deblock filtering while processing said decoded reconstructed video information.

12. The video information processing system of claim 11 , wherein said video decoder is configured to decode an input encoded bitstream into said decoded reconstructed video information and to retrieve control information in said encoded bitstream associated with said decoded reconstructed video information, and wherein said control information indicates disabling chroma deblock filtering and enabling luma deblock filtering.

13. The video information processing system of claim 8 , wherein said processing circuit comprises a memory which stores said video information, and wherein said deblocking filter comprises a post processor for filtering said video information.

14. The video information processing system of claim 8 , wherein said deblocking filter comprises:

a luma deblocking filter which deblock filters said luma component;

a chroma deblocking filter which deblock filters said chroma component; and

control logic which is configured to selectively enable and disable said chroma deblocking filter while said luma deblocking filter is enabled.

15. The video information processing system of claim 8 , wherein said deblocking filter comprises:

a memory for storing said video information; and

a processor, coupled to said memory, wherein said processor is configured to perform luma deblock filtering and chroma deblock filtering;

wherein said processor selectively disables chroma deblock filtering.

16. The video information processing system of claim 8 , wherein said processing circuit comprises a video encoder which encodes said video information into at least one macroblock comprising deblocking filter control information indicating disabling chroma deblock filtering while enabling luma deblock filtering.

17. The video information processing system of claim 8 , wherein said processing circuit comprises a video decoder which decodes at least one macroblock of encoded information while chroma deblock filtering is disabled and while luma deblock filtering is enabled.

18. The video information processing system of claim 8 , wherein said said deblocking filter comprises a blue luma difference deblocking filter and a red luma difference deblocking filter for chroma deblock filtering, and wherein said deblocking filter is configured to enable and disable said blue and red luma difference deblocking filters.

19. A method of deblock filtering at least one macroblock of video information by a video processing system, comprising:

receiving at least one macroblock of unfiltered luma information and unfiltered chroma information;

disabling chroma deblock filtering for the at least one macroblock;

deblock filtering the unfiltered luma information to provide filtered luma information; and

combining the filtered luma information with the unfiltered chroma information into output filtered video information.

20. The method of claim 19 , wherein said disabling chroma deblock filtering comprises decoupling at least one chroma deblocking filter.

21. The method of claim 20 , wherein said decoupling a chroma deblocking filter comprises decoupling an input and an output of the at least one chroma deblocking filter.

22. The method of claim 19 , wherein said disabling chroma deblock filtering comprises disabling at least one chroma deblocking filter.

23. The method of claim 19 , further comprising decoding a deblock filter control signal into a chroma deblock filtering disable signal.

24. The method of claim 19 , further comprising encoding the at least macroblock of output filtered video information to include deblocking filter control information which indicates chroma deblock filtering is disabled and luma deblock filtering is enabled for the at least one macroblock.

25. The method of claim 19 , further comprising decoding the at least one macroblock of output filtered video information while chroma deblock filtering is disabled and while luma deblock filtering is enabled.

26. The method of claim 19 , wherein said disabling chroma deblock filtering comprises disabling at least one of blue luma difference deblock filtering and red luma difference deblock filtering.

Assignments (22)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042985 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0387 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051030/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042762 FRAME 0145. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051145/0184 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050745/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042762/0145 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042985/0001 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
PATENT RELEASE Recorded Aug 17, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 039707/0471 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12092129 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Jul 14, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039361/0212 →
SECURITY AGREEMENT SUPPLEMENT Recorded Mar 7, 2016
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ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 7, 2016
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ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 7, 2016
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To: NORTH STAR INNOVATIONS INC.
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PATENT RELEASE Recorded Dec 21, 2015
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From: FREESCALE SEMICONDUCTOR, INC.
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SUPPLEMENT TO IP SECURITY AGREEMENT Recorded May 4, 2015
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To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
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ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 5, 2015
From: HE, ZHONGLI
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