Atomic rights in a distributed memory system
View Patent ↗According to one embodiment, a memory system includes a plurality of memories, a plurality of first processing units, and a second processing unit. The plurality of first processing units are respectively connected to one of the memories. The second processing unit sequentially distributes a plurality of first data inputted externally sequentially to the plurality of first processing units. Each of the first processing units outputs first data distributed thereto to the one of the memories. The second processing unit, until finishing transmission of a second data to one of the first processing units, keeps the others of the first processing units standing by outputting already-distributed first data. The second data is a last data from among the plurality of first data inputted externally.
1. A memory system comprising:
a plurality of memories;
a plurality of first processing circuits, each of the plurality of first processing circuits being connected to at least one of the memories; and
a second processing circuit that sequentially distributes, to the plurality of first processing circuits, a plurality of items of first data inputted sequentially from an external device,
wherein each of the first processing circuits outputs the first data distributed thereto to the at least one of the memories, and
wherein the second processing circuit, until finishing transmission of second data to one of the first processing circuits, prevents the others of the first processing circuits from outputting the first data distributed already, the second data being a last item of the first data inputted from the external device.
2. The memory system according to claim 1 , wherein the second processing circuit transmits third data to the others of the first processing circuits at the same time that the second processing circuit transmits the second data to the one of the first processing circuits, and
wherein after receiving the second data or the third data, each of the first processing circuits starts the outputting.
3. The memory system according to claim 2 , wherein the second processing circuit adds the third data to a last item of the first data to be distributed to each of the others of the first processing circuits.
4. The memory system according to claim 1 , further comprising a third processing circuit that causes each of the first processing circuits to cancel the outputting while the first processing circuits are prevented from the outputting.
5. The memory system according to claim 4 , wherein in a case where an error occurs in input of the first data before the first processing circuits start the outputting, the third processing circuit resets the second processing circuit.
6. The memory system according to claim 3 , wherein the second processing circuit transmits the first data as fourth data to each of the first processing circuits, each item of the fourth data including a predetermined number of items of the first data, and
wherein the second processing circuit transmits an item of the fourth data including the item of the first data to which the third data is added to each of the others of the first processing circuits at the same time that the second processing circuit transmits an item of the fourth data including the second data to the one of the first processing circuits.
7. The memory system according to claim 6 , wherein the second processing circuit comprises a buffer for creating the fourth data.
8. The memory system according to claim 1 , comprising a plurality of the second processing circuits, wherein each of the plurality of second processing circuits processes a respective one of different write commands, each of the write commands requesting to write a plurality of items of the first data.
9. The memory system according to claim 1 , wherein each of the plurality of memories comprises one or more nonvolatile memory chips.
10. The memory system according to claim 9 , wherein each of the nonvolatile memory chips includes a NAND flash memory.
11. A memory system comprising:
a plurality of first processing circuits, each of the plurality of first processing circuits being connected to at least one of a plurality of memories and which output first data to the at least one of the memories; and
a second processing circuit that sequentially distributes, to the plurality of first processing circuits, a plurality of items of the first data inputted sequentially from an external device and that, until finishing transmission of second data to one of the first processing circuits, prevents the others of the first processing circuits from outputting the first data already distributed, the second data being a last item of the first data inputted from the external device.
12. The memory system according to claim 11 , wherein the plurality of items of the first data are data which are requested to be written by a write command, each of the plurality of items of the first data is inputted by a packet individually, and the second data is an item of the first data inputted by a last packet.