IP Library Granted Patent US 9,807,204
Granted Patent B2
US 9,807,204 · App. 14/640,959 · Granted Oct 31, 2017

Optimized message processing

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Quick Facts
Patent No.
US 9,807,204
App. No.
14/640,959
Granted
Oct 31, 2017
Kind
B2
Abstract

Methods, systems, and computer readable media for optimized message processing are disclosed. According to one exemplary method, the method includes receiving a message including header information. The method further includes determining, using the header information, whether a fast-path identification rule exists for identifying the message. The method also includes in response to determining that the fast-path identification rule does not exist, identifying the message using slow-path processing, determining the fast-path identification rule using the slow-path processing, and storing the fast-path identification rule in a memory.

Claims (45)

1. A method for optimized message processing, the method comprising:

receiving a message including header information;

determining, using the header information, that a fast-path identification rule does not exist for identifying a protocol of the message; and

in response to determining that the fast-path identification rule does not exist:

identifying the protocol of the message using slow-path processing,

determining the fast-path identification rule using the slow-path processing, wherein the fast-path identification rule includes a mask that indicates locations of protocol-identifying data in messages associated with the protocol, and

storing the fast-path identification rule in a memory.

2. The method of claim 1 comprising:

in response to determining that the fast-path identification rule does exist, identifying, using fast-path processing, the protocol of the message using the fast-path identification rule.

3. The method of claim 1 wherein determining the fast-path identification rule using the slow-path processing includes identifying the protocol of the message using a protocol tree and generating the fast-path identification rule using the protocol tree.

4. The method of claim 1 wherein determining the fast-path identification rule using the slow-path processing includes selecting the fast-path identification rule from among a plurality of predefined fast-path identification rules.

5. The method of claim 1 wherein the mask is a bitmask, a multi-bitmask, a byte mask, or a multi-byte mask.

6. The method of claim 1 wherein prior to storing the fast-path identification rule in the memory, deleting another fast-path identification rule stored in the memory.

7. The method of claim 2 wherein identifying the protocol of the message using the fast-path identification rule includes identifying, using the fast-path identification rule, that the message includes one or more header types or protocols.

8. The method of claim 2 wherein the slow-path processing or the fast-path processing identifies the message using serial processing or parallel processing.

9. The method of claim 1 wherein the fast-path identification rule is one of a plurality of fast-path identification rules stored in the memory.

10. The method of claim 9 wherein the plurality of fast-path identification rules are indexed, sorted, or processed in a particular order.

11. The method of claim 2 wherein the slow-path processing or the fast-path processing is implemented using software executing on a processor, a computing platform, a logic device, a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), or an application specific integrated circuit (ASIC).

12. A system for optimized message processing, the system comprising:

a slow-path processing module configured to identify a protocol of a message using slow-path processing; and

a message identification module (MIM), wherein each of the slow-path processing module and the MIM is implemented using software executing on a processor, a computing platform, a logic device, a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), or an application specific integrated circuit (ASIC), wherein the MIM is configured to:

receive a message including header information;

determine, using the header information, that a fast-path identification rule does not exist for identifying a protocol of the message; and

in response to determining that the fast-path identification rule does not exist:

identify the protocol of the message using the slow-path processing module,

determine the fast-path identification rule using the slow-path processing module, wherein the fast-path identification rule includes a mask that indicates locations of protocol-identifying data in messages associated with the protocol, and

store the fast-path identification rule in a memory.

13. The system of claim 12 comprising:

a fast-path processing module configured to identify the protocol of the message using the fast-path identification rule.

14. The system of claim 12 wherein the MIM is configured to determine the fast-path identification rule using the slow-path processing module by identifying the protocol of the message using a protocol tree associated with the slow-path processing module and generating the fast-path identification rule using with the protocol tree.

15. The system of claim 12 wherein the MIM is configured to select the fast-path identification rule from among a plurality of predefined fast-path identification rules.

16. The system of claim 12 wherein the mask is a bitmask, a multi-bitmask, a byte mask, or a multi-byte mask.

17. The system of claim 12 wherein the MIM is configured to delete, prior to storing the fast-path identification rule in the memory, another fast-path identification rule stored in the memory.

18. The system of claim 13 wherein the fast-path processing module is configured to identify, using the fast-path identification rule, that the message includes one or more header types or protocols.

19. The system of claim 13 wherein the slow-path processing module or the fast-path processing module is configured to identify the protocol of the message using serial processing or parallel processing.

20. The system of claim 12 wherein the fast-path identification rule is one of a plurality of fast-path identification rules stored in the memory.

21. The system of claim 18 wherein the plurality of fast-path identification rules are indexed, sorted, or processed in a particular order.

22. The system of claim 13 wherein the fast-path processing module is implemented using software executing on a processor, a computing platform, a logic device, a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), or an application specific integrated circuit (ASIC).

23. A non-transitory computer readable medium comprising computer executable instructions embodied in the computer readable medium that when executed by a processor of a computer cause the computer to perform steps comprising:

receiving a message including header information;

determining, using the header information, that a fast-path identification rule does not exist for identifying a protocol of the message; and

in response to determining that the fast-path identification rule does not exist:

identifying the protocol of the message using slow-path processing,

determining the fast-path identification rule using the slow-path processing, wherein the fast-path identification rule includes a mask that indicates locations of protocol-identifying data in messages associated with the protocol; and

storing the fast-path identification rule in a memory.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 19, 2018
From: KEYSIGHT TECHNOLOGIES SINGAPORE (HOLDINGS) PTE. LTD.
To: KEYSIGHT TECHNOLOGIES SINGAPORE (SALES) PTE. LTD.
Reel/Frame 048225/0065 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 18, 2017
From: IXIA
To: KEYSIGHT TECHNOLOGIES SINGAPORE (HOLDINGS) PTE. LTD.
Reel/Frame 044222/0695 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 10, 2015
From: BERGERON, MATTHEW R.
To: IXIA
Reel/Frame 035377/0755 →