Reduction of power use during address translation via selective refresh operations
According to one embodiment, a memory system is provided with a nonvolatile memory, a controller, a volatile memory and an address translation table. The address translation table includes a high level and a plurality of low levels. The high level indicates positions in the nonvolatile memory in which the low levels are recorded. The low levels indicate positions in the nonvolatile memory in which data is recorded. The controller holds the high level of the address translation table in the first area of the volatile memory, and shuts off the supply of power to the second area of the volatile memory based on a transition from a normal-power state to a low-power state.
1. A memory system comprising:
a nonvolatile memory having a plurality of physical blocks, and each of the physical blocks being an erasure unit;
a volatile memory including a first area and a second area, the volatile memory being a single memory device to which a supply of power is configured to be shut off either to the first area or the second area selectively, and the first area and the second area being capable of being refreshed selectively; and
a controller circuit configured to translate a logical address of write data supplied from a host into a physical address to access the nonvolatile memory on the basis of an address translation table, the address translation table being configured to translate the logical address into the physical address, and including first data and second data, the first data indicating positions in the nonvolatile memory in which the second data are stored, the second data indicating positions in the nonvolatile memory in which data are stored,
wherein the controller circuit is configured to store the first data of the address translation table in the first area of the volatile memory, to store the second data of the address translation table in the second area of the volatile memory, to refresh the first area and the second area of the volatile memory during a first power mode, and to refresh only the first area of the volatile memory during a second power mode, wherein the first data correspond to upper bits of the logical address of the write data and the second data correspond to lower bits of the logical address of the write data, and
wherein the power is supplied to the first area and the second area during the first power mode, and the power is supplied to the first area during the second power mode.
2. The system according to claim 1 , wherein the first area and the second area correspond to memory cell arrays contained in the single memory device, which is configured to shut off power only to the second area of the volatile memory during the second power mode.
3. The system according to claim 1 , wherein the controller circuit shuts off the supply of power to the second area of the volatile memory on the basis of a transition from the first power mode to the second power mode.
4. The system according to claim 1 , wherein the first power mode is a normal power state, and the second power mode is a low power state.
5. The system according to claim 4 , wherein
a part of the second data of the address translation table that have most recently been used are assigned a higher priority; and
the controller circuit is further configured to store the part of the second data of the address translation table with higher priority in the first area of the volatile memory.
6. The system according to claim 5 , wherein
the controller circuit is further configured to store the part of the second data of the address translation table with higher priority in the first area of the volatile memory during the second power mode.
7. The system according to claim 1 , wherein the controller circuit is further configured to store a part of the second data of the address translation table in the first area of the volatile memory.
8. The system according to claim 1 , further comprising:
a first table indicating correspondence between a logical block and a plurality of groups of physical blocks in the nonvolatile memory, the logical block indicating the groups of physical blocks; and
a valid data amount table holding data indicative of a valid data amount in the logical block,
wherein the controller circuit is further configured to store, in the first area of the volatile memory, at least one of the first table and the valid data amount table.
9. The system according to claim 1 , further comprising a second table indicating defective portions in the nonvolatile memory,
wherein
the second table includes first data and second data, the first data of the second table indicating positions in the nonvolatile memory and the volatile memory in which the second data of the second table are stored; and
the controller circuit is further configured to store the first data of the second table in the first area of the volatile memory.
10. The system according to claim 9 , wherein
the second data of the second table that have most recently been used are assigned a higher priority; and
the controller circuit is further configured to store the second data of the second table with higher priority in the first area of the volatile memory.
11. The system according to claim 10 , wherein
the controller circuit is further configured to store the second data of the second table with higher priority in the first area of the volatile memory during the second power mode.
12. The system according to claim 9 , wherein the controller circuit is further configured to store data with higher priority in the first area of the volatile memory,
wherein data indicating the defective portions of the nonvolatile memory used to store the second data of the address translation table has higher priority compared to data indicating the defective portions of the nonvolatile memory used to store user data.
13. The system according to claim 9 , wherein when the host requests a transition to the second power mode, or when the host does not issue a request to read user data for a predetermined period of time, the controller circuit is further configured to store in the first area of the volatile memory,
data indicative of a defective portion of a physical block to which user data requested by the host is to be written,
data indicative of a defective portion of a physical block to which user data is moved by garbage collection and is to be written, and
data indicative of a defective portion of a physical block to which the address translation table is to be written.
14. The system according to claim 1 , wherein the controller circuit is further configured to transition to the second power mode when there is no data access request from the host for a predetermined period of time.
15. The system according to claim 1 , wherein the controller circuit is further configured to transition to the second power mode in response to a host request.
16. The system according to claim 1 , further comprising a second table, the second table including first data and second data, the first data of the second table being stored in the first area of the volatile memory and indicating positions in the nonvolatile memory and the volatile memory in which the second data of the second table is stored, the second data of the second table indicating defective portions in the nonvolatile memory,
the nonvolatile memory comprises:
a first area;
a second area; and
a third area,
wherein
the first area of the nonvolatile memory storing at least user data;
the defective portions in the first area of the nonvolatile memory are indicated by the second data of the second table, and the second area of the nonvolatile memory stores the second data of the second table; and
the defective portions in the second area of the nonvolatile memory are indicated by the first data of the second table, and the third area of the nonvolatile memory stores the first data of the second table.
17. The system according to claim 1 , wherein the controller circuit is further configured to store, in the first area of the volatile memory, data indicative of a state of garbage collection during the second power mode.
18. The system according to claim 1 , wherein when the supply of power from an external power supply is shut off, the controller circuit is further configured to shut off the supply of power to the second area of the volatile memory that stores data already stored in the nonvolatile memory.
19. A memory system comprising:
a nonvolatile memory having a plurality of physical blocks, and each of the physical blocks being an erasure unit;
a first circuit configured to receive a read request and a write request of data designated by a logical address, from a host;
a volatile memory including a first area and a second area, the volatile memory being a single memory device to which a supply of power is configured to be shut off either to the first area or the second area selectively, and the first area and the second area being capable of being refreshed selectively; and
a second circuit configured to translate a logical address of write data into a physical address to access the nonvolatile memory on the basis of a request from the first circuit and an address translation table, the address translation table being configured to translate the logical address into the physical address, and including first data and second data, the first data indicating positions in the nonvolatile memory in which the second data are stored, the second data indicating positions in the nonvolatile memory in which data are stored,
wherein the second circuit is configured to store the first data of the address translation table in the first area of the volatile memory, to store the second data of the address translation table in the second area of the volatile memory, to refresh the first area and the second area of the volatile memory during a first power mode, and to refresh only the first area of the volatile memory during a second power mode, wherein the first data correspond to upper bits of the logical address of the write data and the second data correspond to lower bits of the logical address of the write data, and
wherein the power is supplied to the first area and the second area during the first power mode, and the power is supplied to the first area during the second power mode.
20. The system according to claim 19 , wherein the first area and the second area correspond to memory cell arrays contained in the single memory device.
21. The system according to claim 19 , wherein the second circuit is further configured to shut off the supply of power to the second area of the volatile memory on the basis of a transition from the first power mode to the second power mode.
22. The system according to claim 19 , wherein the first power mode is a normal power state, and the second power mode is a low power state.
23. The system according to claim 22 , wherein
a part of the second data of the address translation table that have most recently been used are assigned to a higher priority; and
the second circuit is further configured to store the part of the second data of the address translation table with higher priority in the first area of the volatile memory.
24. The system according to claim 23 , wherein
the second circuit is further configured to store the part of the second data of the address translation table with higher priority during the second power mode.
25. The system according to claim 19 , wherein the second circuit is further configured to store a part of the second data of the address translation table in the first area of the volatile memory.
26. The system according to claim 19 , further comprising:
a first table indicating correspondence between a logical block and a plurality of groups of physical blocks in the nonvolatile memory, the logical block indicating a structure of the groups of physical blocks; and
a valid data amount table holding data indicative of a valid data amount in the logical block,
wherein the second circuit is further configured to store, in the first area of the volatile memory, at least one of the first table and the valid data amount table.
27. The system according to claim 19 , further comprising a second table indicating defective portions in the nonvolatile memory,
wherein
the second table includes first data and second data, the first data of the second table indicating positions in the nonvolatile memory and the volatile memory in which the second data of the second table are stored; and
the second circuit is further configured to store the first data of the second table in the first area of the volatile memory.
28. The system according to claim 27 , wherein
the second data of the second table that have most recently been used are assigned to a higher priority; and
the second circuit is further configured to store the second data of the second table with higher priority in the first area of the volatile memory.
29. The system according to claim 28 , wherein
the second circuit is further configured to store the second data of the second table with higher priority in the first area of the volatile memory during the second power mode.
30. The system according to claim 27 , wherein the second circuit is further configured to store data with higher priority in the first area of the volatile memory,
wherein data indicating the defective portions of the nonvolatile memory used to store the second data of the address translation table has higher priority compared to data indicating the defective portions of the nonvolatile memory used to store user data.
31. The system according to claim 27 , wherein when the host requests a transition to the second power mode, or when the host does not issue a request to read user data for a predetermined period of time, the second circuit is further configured to store in the first area of the volatile memory,
data indicative of a defective portion of a physical block to which user data requested by the host is to be written,
data indicative of a defective portion of a physical block to which user data is moved by garbage collection and to be written, and
data indicative of a defective portion of a physical block to which the address translation table is to be written.
32. The system according to claim 19 , wherein the second circuit is further configured to transition to the second power mode when there is no data access request from the host for a predetermined period of time.
33. The system according to claim 19 , wherein the second circuit is further configured to transition to the second power mode in response to a host request.
34. The system according to claim 19 , further comprising a second table, the second table including first data and second data, the first data of the second table being stored in the first area of the volatile memory and indicating positions in the nonvolatile memory and the volatile memory in which the second data of the second table is stored, the second data of the second table indicating defective portions in the nonvolatile memory,
the nonvolatile memory comprises:
a first area;
a second area; and
a third area,
wherein
the first area of the nonvolatile memory storing at least user data;
the defective portions in the first area of the nonvolatile memory are indicated by the second data of the second table, and the second area of the nonvolatile memory stores the second data of the second table; and
the defective portions in the second area of the nonvolatile memory are indicated by the first data of the second table, and the third area of the nonvolatile memory stores the first data of the second table.
35. The system according to claim 19 , wherein the second circuit is further configured to store, in the first area of the volatile memory, data indicative of a state of garbage collection during the second power mode.
36. The system according to claim 19 , wherein when the supply of power from an external power supply is shut off, the second circuit is further configured to shut off the supply of power to the second area of the volatile memory that stores data already stored in the nonvolatile memory.
37. A control method of a memory system based on an address translation table comprising:
translating a logical address of write data into a physical address to access a nonvolatile memory;
storing first data of the address translation table in a first area of a volatile memory;
storing second data of the address translation table in a second area of the volatile memory, the first data indicating positions in the nonvolatile memory in which the second data of the address translation table are stored, the second data indicating positions in the nonvolatile memory in which the write data are stored, the volatile memory being a single memory device to which a supply of power is configured to be shut off either to the first area or the second area selectively, the first area and the second area being capable of being refreshed selectively, and the first data corresponding to upper bits of the logical address of the write data and the second data corresponding to lower bits of the logical address of the write data;
refreshing the first area and a second area of the volatile memory during a first power mode; and
refreshing only the first area of the volatile memory during a second power mode,
wherein the power is supplied to the first area and the second area during the first power mode, and the power is supplied to the first area during the second power mode.
38. The method according to claim 37 , wherein the first area and the second area correspond to memory cell arrays contained in the single memory device.
39. The method according to claim 37 , further comprising:
shutting off the supply of power to the second area of the volatile memory on the basis of a transition from the first power mode to the second power mode.
40. The method according to claim 37 , wherein the first power mode is a normal power state, and the second power mode is a low power state.
41. The method according to claim 37 , further comprising:
storing a part of the second data of the address translation table in the first area of the volatile memory.
42. The method according to claim 37 , further comprising:
storing, during the second power mode, at least one of a first table, a valid data amount table, and a second table, in the first area of the volatile memory,
the first table indicating correspondence between a logical block and a plurality of groups of physical blocks in the nonvolatile memory, the logical block indicating a structure of the groups of physical blocks in the nonvolatile memory;
the valid data amount table holding data indicative of a valid data amount in the logical block; and
the second table indicating defective portions of the nonvolatile memory,
wherein the second table includes first data and second data, the first data of the second table indicating positions in the nonvolatile memory and the volatile memory in which the second data of the second table are stored.