IP Library Patent Application 14642530
Patent Application
App. No. 14/642,530

SEMICONDUCTOR MEMORY DEVICE

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Quick Facts
Patent No.
US None
App. No.
14/642,530
Abstract

According to one embodiment, a semiconductor memory device includes: a first component including a controller which issues an instruction complying with a NAND interface; and a second component including a first NAND flash memory which is controlled by the instruction, the second component being removable from the first component.

Claims (34)

1 . A semiconductor memory device comprising:

a first component including a controller which issues an instruction complying with a NAND interface; and

a second component including a first NAND flash memory to be controlled by the instruction, the second component being removable from the first component.

2 . The device according to claim 1 , wherein the first component further includes a second NAND flash memory to be controlled by the instruction.

3 . The device according to claim 2 , wherein the controller stores data of a block whose rewrite count is not less than a reference value in the first NAND flash memory and data of a block whose rewrite count is less than the reference value in the second NAND flash memory.

4 . The drive according to claim 2 , wherein the controller writes data to the first NAND flash memory, and moves the data of a block in the first NAND flash memory whose rewrite count is less than the reference value to the second NAND flash memory.

5 . The drive according to claim 2 , wherein the controller writes data to the first NAND flash memory or the second NAND flash memory, moves the data of a block in the first NAND flash memory whose rewrite count is less than the reference value to the second NAND flash memory, and moves the data of a block in the second NAND flash memory whose rewrite count is not less than the reference value to the first NAND flash memory.

6 . The device according to claim 3 , wherein the controller changes the reference value according to free spaces of the first NAND flash memory and the second NAND flash memory.

7 . The device according to claim 1 , wherein the controller initializes to the first NAND flash memory, after the second component is inserted into the first component.

8 . The device according to claim 1 , wherein a wiring for input/output signal between the controller and the first NAND flash memory is a serial wiring.

9 . The device according to claim 2 , wherein a wiring for input/output signal between the controller and the second NAND flash memory is a serial wiring.

10 . The device according to claim 2 , wherein

the first NAND flash memory comprises a NAND flash memory of one of an eMLC type and an SLC type, and

the second NAND flash memory comprises a NAND flash memory of a TLC type.

11 . The device according to claim 1 , wherein the semiconductor memory device comprises a solid state drive.

12 . A semiconductor memory device comprising:

a first circuit board;

a second circuit board being different from the first circuit board;

a first NAND flash memory mounted in the first circuit board;

a second NAND flash memory mounted in the second circuit board; and

a controller mounted in the second circuit board,

wherein wirings for input/output signal between the controller and the first NAND flash memory and between the controller and the second NAND flash memory are serial wirings.

13 . The device according to claim 12 , wherein the serial wirings are differential serial wirings.

14 . The device according to claim 12 , further comprising a connector connecting the first circuit board and the second circuit board.

15 . The device according to claim 12 , wherein

a wiring structure between the controller and the first NAND flash memory is a same as a wiring structure between the controller and the second NAND flash memory.

16 . The device according to claim 12 , wherein

a communication mode between the controller and the first NAND flash memory is a same as a communication mode between the controller and the second NAND flash memory.

17 . A solid state drive comprising:

a first component including a controller; and

a second component including a first nonvolatile semiconductor memory to be controlled by the controller, the second component being removable from the first component.

18 . The drive according to claim 17 , wherein the first component further includes a second nonvolatile semiconductor memory to be controlled by the controller.

19 . The device according to claim 17 , wherein a wiring for input/output signal between the controller and the first nonvolatile semiconductor memory is a serial wiring.

20 . The device according to claim 18 , wherein a wiring for input/output signal between the controller and the second nonvolatile semiconductor memory is a serial wiring.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 14, 2017
From: KABUSHIKI KAISHA TOSHIBA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 043194/0382 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 9, 2015
From: KURITA, YOICHIRO; SUTO, HIROYUKI; KIMURA, FUMINORI
To: KABUSHIKI KAISHA TOSHIBA
Reel/Frame 035119/0729 →