Semiconductor device including refresh circuit for memory cell

1. A semiconductor device comprising:

a memory cell;

a sense amplifier circuit;

a latch circuit;

a first switch;

a second switch; and

a driver circuit,

wherein the sense amplifier circuit, the latch circuit, the first switch, and the second switch operate in a refresh operation of the memory cell,

wherein the memory cell includes a first transistor, a second transistor, and a capacitor,

wherein the first transistor includes an oxide semiconductor in a channel formation region,

wherein one of a source and a drain of the first transistor is electrically connected to a first wiring,

wherein the other of the source and the drain of the first transistor is electrically connected to one terminal of the capacitor,

wherein the other of the source and the drain of the first transistor is electrically connected to a gate of the second transistor,

wherein one of a source and a drain of the second transistor is electrically connected to the first wiring,

wherein a gate of the first transistor is electrically connected to a second wiring,

wherein the other terminal of the capacitor is electrically connected to a third wiring,

wherein the other of the source and the drain of the second transistor is electrically connected to a fourth wiring,

wherein a first input terminal of the sense amplifier circuit is electrically connected to the first wiring,

wherein an output terminal of the sense amplifier circuit is directly connected to an input terminal of the latch circuit,

wherein the output terminal of the sense amplifier circuit is directly connected to a fifth wiring which is different from the first wiring,

wherein an output terminal of the latch circuit is electrically connected to one terminal of the first switch,

wherein the other terminal of the first switch is electrically connected to the first wiring,

wherein one terminal of the second switch is electrically connected to the first wiring,

wherein the other terminal of the second switch is electrically connected to the driver circuit,

wherein the fifth wiring is directly connected to the driver circuit, and

wherein the first transistor and the second transistor share the first wiring.

2. The semiconductor device according to claim 1 , in the refresh operation,

wherein a first potential is a potential of the first wiring which reflects a potential of the gate of the second transistor,

wherein the first potential is input to the first input terminal of the sense amplifier circuit,

wherein the sense amplifier circuit outputs a signal to the latch circuit when the first potential is input to the sense amplifier circuit,

wherein an output of the sense amplifier circuit is input to the latch circuit, and a latch operation is performed, and

wherein a second potential output from the latch circuit is input to the gate of the second transistor and the one terminal of the capacitor through the first switch, the first wiring, and the first transistor.

3. The semiconductor device according to claim 1 , wherein the oxide semiconductor included in the first transistor comprises indium and zinc.

4. The semiconductor device according to claim 1 , wherein the latch circuit includes an inverter.

5. The semiconductor device according to claim 1 , wherein the latch circuit includes a first inverter, a second inverter, a third inverter, a fourth inverter, a first analog switch, and a second analog switch.

6. The semiconductor device according to claim 5 , wherein the first analog switch is electrically connected to the output terminal of the sense amplifier circuit and the first inverter is electrically connected to the first analog switch.

7. The semiconductor device according to claim 6 , wherein the first inverter and the second inverter are configured to form a loop.

8. The semiconductor device according to claim 7 , wherein the first inverter is electrically connected to the first switch.

9. The semiconductor device according to claim 8 , wherein the second analog switch is electrically connected to the second inverter and the first analog switch.

10. The semiconductor device according to claim 9 , wherein the third inverter is electrically connected to the fourth inverter, and the fourth inverter is electrically connected to the first analog switch and the second analog switch.

11. The semiconductor device according to claim 1 , wherein the number of the sense amplifier circuit is the same as the number of the latch circuit.