IP Library Granted Patent US 9,728,459
Granted Patent B2
US 9,728,459 · App. 14/647,071 · Granted Aug 8, 2017

Method for singulating an assemblage into semiconductor chips, and semiconductor chip

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Quick Facts
Patent No.
US 9,728,459
App. No.
14/647,071
Granted
Aug 8, 2017
Kind
B2
Abstract

A method for singulating an assemblage ( 1 ) into a plurality of semiconductor chips ( 10 ) is specified, wherein an assemblage comprising a carrier ( 4 ), a semiconductor layer sequence ( 2 ) and a metallic layer ( 3 ) is provided. Separating trenches ( 45 ) are formed in the carrier. The assemblage is subjected to mechanical loading, with the result that the metallic layer breaks along the separating trenches and the assemblage is singulated into semiconductor chips, wherein the singulated semiconductor chips each have part of the semiconductor layer sequence, of the carrier and of the metallic layer. A semiconductor chip ( 10 ) is furthermore specified.

Claims (26)

1. A method for singulating an assemblage into a plurality of semiconductor chips comprising the following steps:

a) providing an assemblage comprising a carrier, a semiconductor layer sequence and a metallic layer;

b) forming separating trenches in the carrier; and

c) subjecting the assemblage to mechanical loading, with the result that the metallic layer breaks along the separating trenches and the assemblage is singulated into semiconductor chips,

wherein the singulated semiconductor chips each have part of the semiconductor layer sequence, of the carrier and of the metallic layer,

wherein the metallic layer is arranged between the semiconductor layer sequence and the carrier,

wherein after step b) the metallic layer is the only layer of the assemblage via which carrier bodies of the carrier are still mechanically stably connected to one another and

wherein the metallic layer remains in the singulated and completed semiconductor chips.

2. The method according to claim 1 , wherein the mechanical loading is effected by means of a pressure action on the assemblage in a direction running obliquely or perpendicularly to a main surface of the assemblage.

3. The method according to claim 1 , wherein the metallic layer extends over the whole area of the assemblage before step c).

4. The method according to claim 1 , wherein the separating trenches are formed by means of a chemical method.

5. The method according to claim 1 , wherein the separating trenches extend completely through the carrier after step b).

6. The method according to claim 1 , wherein steps b) and c) are carried out from opposite sides of the assemblage.

7. The method according to claim 1 , wherein the assemblage is exposed to a mechanical stress at least along a lateral direction before step c).

8. The method according to claim 1 , wherein the assemblage is fixed to an auxiliary carrier before singulation and the semiconductor chips are present on the auxiliary carrier for further processing after singulation.

9. The method according to claim 8 , wherein the semiconductor layer sequence, after step b), is fixed to the auxiliary carrier at that side of the assemblage from which the separating trenches are introduced into the carrier.

10. The method according to claim 1 , wherein the assemblage is exposed to a liquid jet or gas jet in step c).

11. The method according to claim 10 , wherein carbon dioxide is used as jet medium.

12. The method according to claim 1 , wherein the assemblage is subjected to a pressure wave in step c).

13. A method for singulating an assemblage into a plurality of semiconductor chips comprising the following steps:

a) providing an assemblage comprising a carrier, a semiconductor layer sequence and a metallic layer;

b) forming separating trenches in the carrier; and

c) subjecting the assemblage to mechanical loading, with the result that the metallic layer breaks along the separating trenches and the assemblage is singulated into semiconductor chips,

wherein the singulated semiconductor chips each have part of the semiconductor layer sequence, of the carrier and of the metallic layer,

wherein the separating trenches extend completely through the carrier after step b), and

wherein the assemblage is exposed to a mechanical stress at least along a lateral direction after step b) and before step c).

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 3, 2020
From: OSRAM OPTO SEMICONDUCTORS GMBH
To: OSRAM OLED GMBH
Reel/Frame 051467/0906 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 5, 2016
From: KAEMPF, MATHIAS
To: OSRAM OPTO SEMICONDUCTORS GMBH
Reel/Frame 038199/0035 →