IP Library Granted Patent US 10,023,974
Granted Patent B2
US 10,023,974 · App. 14/648,256 · Granted Jul 17, 2018

Substrates for semiconductor devices

Inventors: Timothy Mollart (Oxfordshire, GB); Quanzhong Jiang (Somerset, GB); Michael John Edwards (Somerset, GB); Duncan Allsopp (Somerset, GB); Christopher Rhys Bowen (Somerset, GB); Wang Nang Wang (Somerset, GB)
C30B25/18C23C16/27C30B25/183C30B29/04C30B29/36C30B29/40C30B29/403C30B29/406H01L21/0245H01L21/0254H01L21/0262H01L21/02376H01L21/02428H01L21/02433H01L21/02513H01L21/02521H01L21/02538H01L23/3732H01L2924/0002
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Quick Facts
Patent No.
US 10,023,974
App. No.
14/648,256
Granted
Jul 17, 2018
Kind
B2
Abstract

A method of fabricating a composite semiconductor component comprising: (i) providing a bowed substrate comprising a wafer of synthetic diamond material having a thickness t d , the bowed substrate being bowed by an amount B and comprising a convex face and a concave face; (ii) growing a layer of compound semiconductor material on the convex face of the bowed substrate via a chemical vapour deposition technique at a growth temperature T to form a bowed composite semiconductor component comprising the layer of compound semiconductor material of thickness t sc on the convex face of the bowed substrate, the compound semiconductor material having a higher average thermal expansion coefficient than the synthetic diamond material between the growth temperature T and room temperature providing a thermal expansion mismatch ΔT ec ; and (iii) cooling the bowed composite semiconductor component, wherein the layer of compound semiconductor material contracts more than the wafer of synthetic diamond material during cooling due to the thermal expansion mismatch ΔT ec , wherein B, t d , t sc , and ΔT ec are selected such that the layer of compound semiconductor material contracts on cooling by an amount which off-sets bowing in the bowed substrate thus pulling the bowed composite semiconductor component into a flat configuration, the layer of compound semiconductor material having a tensile stress after cooling of less than 500 MPa.

Claims (9)

1. A method of fabricating a composite semiconductor component, the method comprising:

(i) disposing a synthetic diamond layer on a wafer and cooling the synthetic diamond layer so that the synthetic diamond layer and wafer form a first bowed substrate;

(ii) removing at least a portion of the wafer of the first bowed substrate so that the first bowed substrate flips to bow in an opposite direction to thereby form a second bowed substrate, the second bowed substrate has a convex face and a concave face;

(iii) growing a layer of compound semiconductor material on the convex face of the second bowed substrate at a growth temperature to form a bowed composite semiconductor component, the compound semiconductor material having a higher average thermal expansion coefficient than the synthetic diamond material between the growth temperature and room temperature; and

(iv) cooling the bowed composite semiconductor component, wherein the layer of compound semiconductor material contracts more than the synthetic diamond layer during cooling due to a thermal expansion mismatch between the compound semiconductor material and a material of the synthetic diamond layer and wherein the layer of compound semiconductor material contracts on cooling by an amount which off-sets bowing in the second bowed substrate thus pulling the bowed composite semiconductor component into a flat configuration.

2. A method according to claim 1 , wherein, after step (iv), the layer of compound semiconductor material has a tensile stress of less than 500 MPa.

3. A method according to claim 1 , wherein a thickness of the synthetic diamond layer is in a range of 25 μm to 450 μm.

4. A method according to claim 1 , wherein the wafer includes a silicon layer and the step of removing at least a portion of the wafer includes removing the silicon layer.

5. A method according to claim 1 , wherein the wafer further includes a first silicon layer, a silicon dioxide layer and a second silicon layer and the step of removing the at least a portion of the wafer includes removing the first silicon layer.

Assignments (4)
CORRECTIVE ASSIGNMENT TO CORRECT THE RECEIVING PARTY DATA PREVIOUSLY RECORDED AT REEL: 041113 FRAME: 0781. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Dec 19, 2018
From: RFHIC CORPORATION
To: RFHIC CORPORATION; AKASH SYSTEMS, INC.
Reel/Frame 047953/0428 →
TECHNOLOGY AGREEMENT. ASSIGNMENT OF INTELLECTUAL PROPERTY FOR COMMERCIAL SATELLITE SYSTEMS, SUBSYSTEMS, MODULES AND DEVICES Recorded Jan 13, 2017
From: RFHIC CORPORATION
To: AKASH SYSTEMS, INC.
Reel/Frame 041113/0781 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 3, 2016
From: ELEMENT SIX TECHNOLOGIES LIMITED
To: RFHIC CORPORATION
Reel/Frame 039916/0411 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 8, 2016
From: ELEMENT SIX LIMITED
To: ELEMENT SIX TECHNOLOGIES LIMITED
Reel/Frame 038838/0958 →
Priority Claims (2)
GB 1222798.9 · Dec 18, 2012 · national
GB 1310039.1 · Jun 5, 2013 · national
Continuity (2)
Provisional Application 61738641 · Dec 18, 2012
Related Publication 20160186362A1 · Jun 30, 2016