Multimode decoder implementation method and device

1. A multi-mode decoder implementation method, comprising:

storing to-be-decoded data according to a predetermined method;

performing an interleaving processing on the stored to be decoded data to obtain an interleaving address; and

based on the interleaving address, using a Radix-4 algorithm architecture, multiplexing a set of maximum a posterior (MAP) decoding units in different standards, and using a parallel processing method to perform a MAP iterative decoding processing on the to-be-decoded data in accordance with standard types;

wherein, said storing to-be-decoded data according to a predetermined method comprises:

in the LTE standard, respectively storing input to-be-decoded data into four groups of RAMs with a depth of 1536 in accordance with processing units (PUs) where the to-be-decoded data are located; wherein each group of RAMs with the depth of 1536 is composed of two RAMs with the depth of 768, which respectively store to-be-decoded data of each PU according to even and odd addresses of each group;

in the UMTS standard and the TD-SCDMA standard, for the input to-be-decoded data, according to the even and odd addresses of each group, in accordance with a length of code block, using a storing method that a group of RAMs with the depth of 1536 is filled up and then a next group of RAMs with the depth of 1536 is filled, wherein each group of RAMs with the depth of 1536 is composed of two RAMs with the depth of 768, and one RAM with the depth of 768 corresponds to data with the odd address, and the other RAM with the depth of 768 corresponds to data with the even address; and

in the WiMAX standard, storing 600 bit pairs corresponding to A/B of each channel of to-be-decoded data into two RAMs with the depth of 768 within the RAM with the depth of 1536, storing 600 bit pairs corresponding to Y of each channel of to-be-decoded data into two RAMs with the depth of 768 within the RAM with the depth of 1536, and storing 600 bit pairs corresponding to W of each channel of to-be-decoded data into two RAMs with the depth of 768 within the RAM with the depth of 1536.

2. The method of claim 1 , wherein said based on the interleaving address, using a Radix-4 algorithm architecture, multiplexing a set of MAP decoding units in different standards, and using a parallel processing method to perform a MAP iterative decoding processing on the to-be-decoded data in accordance with standard types comprises:

using the Radix-4 algorithm architecture, multiplexing a set of MAP decoding units, using a parallel processing method and performing a MAP1 processing on the to-be-decoded data in accordance with the standard types;

based on the interleaving address, using the Radix-4 algorithm architecture, multiplexing a set of MAP decoding units, using a parallel processing method, and performing a MAP2 processing on the to-be-decoded data in accordance with the standard types; and

after meeting an iteration termination condition, terminating MAP iterations and outputting a decoding result.

3. The method of claim 2 , wherein,

the set of MAP decoding units comprises four MAP decoding units;

said using the Radix-4 algorithm architecture, multiplexing a set of MAP decoding units, using a parallel processing method, and performing a MAP1 processing on the to-be-decoded data in accordance with the standard types comprises:

in a Long Term Evolution (LTE) standard and Worldwide Interoperability for Microwave Access (WiMAX) standard, using four MAP decoding units for parallel processing, and using a forward Alpha and backward Beta collision computing method, before a collision, while reading priori information to perform a MAP calculation, sequentially buffering priori information of a sliding window length; after a collision, reading the priori information from a buffer for calculation, and saving priori information obtained from calculation into a priori information storage random access memory (RAM); and

in a Universal Mobile Telecommunications System (UMTS) standard and time division-synchronous code division multiple address (TD-SCDMA) standard, when calculating Gamma, backing up system information at the same time.

4. The method of claim 2 , wherein,

the set of MAP decoding units comprises four MAP decoding units;

said based on the interleaving address, using the Radix-4 algorithm architecture, multiplexing a MAP decoding unit, and using a parallel processing method and performing a MAP2 processing on the to-be-decoded data in accordance with the standard types comprises:

in a LTE standard and WiMAX standard, based on the interleave address, using four MAP decoding units for parallel processing, and using a forward Alpha and backward Beta collision computing method, before a collision, while reading priori information to perform a MAP calculation, sequentially buffering priori information of a sliding window length; after a collision, reading the priori information from a buffer for calculation, and saving priori information obtained from calculation into a priori information storage RAM; and

in a UMTS standard and TD-SCDMA standard, when performing an Alpha and Beta collision calculation, simultaneously reading 4 system bits/check bit 2 /priori information from a storage RAM; and saving 4 priori information/hard judgments obtained from the collision calculation into the storage RAM at the same time.

5. A multi-mode decoder implementation device, comprising:

a storing module, which is configured to store to-be-decoded data according to a predetermined method;

an interleaving module, which is configured to: perform an interleaving processing on the stored to be decoded data to obtain an interleaving address; and

a decoding module, which is configured to: based on the interleaving address, use a Radix-4 algorithm architecture, multiplex a set of maximum a posterior (MAP) decoding units in different standards, use a parallel processing method and perform a MAP iterative decoding processing on the to-be-decoded data in accordance with standard types;

wherein the storing module is configured to store to-be-decoded data according to a predetermined method in a following way:

in the LTE standard, respectively storing input to-be-decoded data into four groups of RAMs with a depth of 1536 in accordance with processing units (PUs) where the to-be-decoded data are located; wherein each group of RAM with the depth of 1536 is composed of two RAMs with the depth of 768, which respectively store to-be-decoded data of each PU according to even and odd addresses of each group;

in the UMTS standard and the TD-SCDMA standard, for the input to-be-decoded data, according to the even and odd addresses of each group, in accordance with a length of code block, using a storing method that a group of RAMs with the depth of 1536 is filled up and then a next group of RAMs with the depth of 1536 is filled, wherein each group of RAMs with the depth of 1536 is composed of two RAMs with the depth of 768, and one RAM with the depth of 768 corresponds to data with the odd address, and the other RAM with the depth of 768 corresponds to data with the even address; and

in the WiMAX standard, storing 600 bit pairs corresponding to A/B of each channel of to-be-decoded data into two RAMs with the depth of 768 within the RAM with the depth of 1536, storing 600 bit pairs corresponding to Y of each channel of to-be-decoded data into two RAMs with the depth of 768 within the RAM with the depth of 1536, and storing 600 bit pairs corresponding to W of each channel of to-be-decoded data into two RAMs with the depth of 768 within the RAM with the depth of 1536.

6. The device of claim 5 , wherein the decoding module comprises:

a MAP1 processing unit, which is configured to: use the Radix-4 algorithm architecture, multiplex a set of MAP decoding units, use a parallel processing method and perform a MAP1 processing on the to-be-decoded data in accordance with the standard types;

a MAP2 processing unit, which is configured to: based on the interleaving address, use the Radix-4 algorithm architecture, multiplex a set of MAP decoding units, use a parallel processing method, and perform a MAP2 processing on the to-be-decoded data in accordance with the standard types; and

a decoding result outputting unit, which is configured to: after meeting an iteration termination condition, terminate MAP iterations and output a decoding result.

7. The device of claim 6 , wherein,

the set of MAP decoding units comprises four MAP decoding units;

the MAP1 processing unit is configured to use the Radix-4 algorithm architecture, multiplex a set of MAP decoding units, use a parallel processing method and perform a MAP1 processing on the to-be-decoded data in accordance with the standard types in a following way:

in a Long Term Evolution (LTE) standard and Worldwide Interoperability for Microwave Access (WiMAX) standard, using four MAP decoding units for parallel processing, and using a forward Alpha and backward Beta collision computing method, before a collision, while reading priori information to perform a MAP calculation, sequentially buffering priori information of a sliding window length; after a collision, reading the priori information from a buffer for calculation, and saving priori information obtained from calculation into a priori information storage random access memory (RAM); and

in a Universal Mobile Telecommunications System (UMTS) standard and time division-synchronous code division multiple address (TD-SCDMA) standard, when calculating Gamma, backing up system information at the same time.

8. The device of claim 6 , wherein,

the set of MAP decoding unit comprises four MAP decoding units;

the MAP2 processing unit is configured to: based on the interleaving address, use the Radix-4 algorithm architecture, multiplex a set of MAP decoding units, use a parallel processing method, and perform a MAP2 processing on the to-be-decoded data in accordance with the standard types in a following way:

in a LTE standard and WiMAX standard, based on the interleave address, using four MAP decoding units for parallel processing, and using a forward Alpha and backward Beta collision computing method, before a collision, while reading priori information to perform a MAP calculation, sequentially buffering priori information of a sliding window length; after a collision, reading the priori information from a buffer for calculation, and saving priori information obtained from calculation into a priori information storage RAM; and

in a UMTS standard and TD-SCDMA standard, when performing an Alpha and Beta collision calculation, simultaneously reading 4 system bits/check bit 2 /priori information from a storage RAM; and saving 4 priori information/hard judgments obtained from the collision calculation into the storage RAM at the same time.