IP Library Granted Patent US 9,852,063
Granted Patent B2
US 9,852,063 · App. 14/656,506 · Granted Dec 26, 2017

Memory device and non-transitory computer readable recording medium

Inventor: Shinichi Kanno (Tokyo, JP)
Assignee: Toshiba Memory Corporation
G06F12/0246G06F2212/1036G06F2212/222G06F2212/7201G06F2212/7209
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Quick Facts
Patent No.
US 9,852,063
App. No.
14/656,506
Granted
Dec 26, 2017
Kind
B2
Abstract

According to one embodiment, a memory device includes a nonvolatile memory, address translation unit, generation unit, and reception unit. The nonvolatile memory includes erase unit areas. Each of the erase unit areas includes write unit areas. The address translation unit generates address translation information relating a logical address of write data written to the nonvolatile memory to a physical address indicative of a write position of the write data in the nonvolatile memory. The generation unit generates valid/invalid information indicating whether data written to the erase unit areas is valid data or invalid data. The reception unit receives deletion information including a logical address indicative of data to be deleted in the erase unit area.

Claims (31)

1. A memory device communicating with an information processing device, the memory device comprising:

a nonvolatile memory including a plurality of erase unit areas, each of the erase unit areas including a plurality of write unit areas;

an address translation unit which generates address translation information relating a logical address of write data written to the nonvolatile memory to a physical address indicative of a write position of the write data in the nonvolatile memory;

a write unit which writes the write data to the write position indicated by the physical address;

a generation unit which generates, based on the address translation information, valid/invalid information indicating whether data written to the plurality of erase unit areas is valid data or invalid data, the valid/invalid information including information relating identification information of the erase unit area to a logical address indicative of the valid data or the invalid data written to the erase unit area;

a selection unit which selects an erase unit area to be subjected to garbage collection from the plurality of erase unit areas;

a transmission unit which generates, based on the valid/invalid information, area information including a logical address indicative of valid data written to the erase unit area to be subjected to garbage collection, and transmits the area information to the information processing device;

a reception unit which receives deletion information including a logical address indicative of data to be deleted amongst the valid data in the erase unit area to be subjected to garbage collection from the information processing device; and

a garbage collection unit which performs garbage collection of the valid data written to the erase unit area to be subjected to garbage collection excluding the data to be deleted.

2. The memory device according to claim 1 , wherein

the valid data is updated data in a case where update of the data written to the nonvolatile memory is performed, and

the invalid data is data which is not updated in the case where the update is performed, and

the data to be deleted is data for which a delete command is issued.

3. The memory device according to claim 1 , wherein

the selection unit selects an erase unit area having an oldest write time from the plurality of erase unit areas as the erase unit area to be subjected to garbage collection.

4. The memory device according to claim 1 , wherein

the selection unit selects the erase unit area to be subjected to garbage collection at random from the plurality of erase unit areas.

5. The memory device according to claim 1 , wherein

the selection unit selects, based on the valid/invalid information, an erase unit area having a largest amount of the invalid data or an erase unit area having an amount of the invalid data larger than a predetermined amount from the plurality of erase unit areas as the erase unit area to be subjected to garbage collection.

6. The memory device according to claim 1 , wherein

the selection unit selects, based on the valid/invalid information and the deletion information, an erase unit area having a largest amount of the invalid data and the data to be deleted or an erase unit area having an amount of the invalid data and the data to be deleted larger than a predetermined amount from the plurality of erase unit areas as the erase unit area to be subjected to garbage collection.

7. The memory device according to claim 1 , further comprising:

a volatile memory which stores the deletion information.

8. A non-transitory computer readable recording medium storing a program causing a computer to function as:

an address translation unit which generates address translation information relating a logical address of write data written to a nonvolatile memory to a physical address indicative of a write position of the write data in the nonvolatile memory, the nonvolatile memory including a plurality of erase unit areas, each of the erase unit areas including a plurality of write unit areas;

a write unit which writes the write data to the write position indicated by the physical address;

a generation unit which generates, based on the address translation information, valid/invalid information indicating whether data written to the plurality of erase unit areas is valid data or invalid data, the valid/invalid information including information relating identification information of the erase unit area to a logical address indicative of the valid data or the invalid data written to the erase unit area;

a selection unit which selects an erase unit area to be subjected to garbage collection from the plurality of erase unit areas;

a transmission unit which generates, based on the valid/invalid information, area information including a logical address indicative of valid data written to the erase unit area to be subjected to garbage collection, and transmits the area information to the information processing device;

a reception unit which receives deletion information including a logical address indicative of data to be deleted amongst the valid data in the erase unit area to be subjected to garbage collection from an information processing device communicating with the computer; and

a garbage collection unit which performs garbage collection of the valid data written to the erase unit area to be subjected to garbage collection excluding the data to be deleted.

Assignments (5)
MERGER Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: K.K. PANGEA
Reel/Frame 055659/0471 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: KIOXIA CORPORATION
Reel/Frame 055669/0001 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: K.K. PANGEA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 055669/0401 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 8, 2017
From: KABUSHIKI KAISHA TOSHIBA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 043529/0709 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 6, 2015
From: KANNO, SHINICHI
To: KABUSHIKI KAISHA TOSHIBA
Reel/Frame 035573/0583 →
Priority Claims (1)
JP 2015-038998 · Feb 27, 2015 · national
Continuity (2)
Provisional Application 62097532 · Dec 29, 2014
Related Publication 20160188459A1 · Jun 30, 2016