Interface circuit executing protocol control in compliance with first and second interface standards
View Patent ↗According to one embodiment, a first module is responsible for protocol control in compliance with a first interface standard. A second module is provided separately from the first module and is responsible for protocol control in compliance with a second interface standard. A third module is responsible for a physical layer shared between the first interface standard and the second interface standard.
1. An interface circuit comprising:
a first module that executes protocol control in compliance with a first interface standard;
a second module that is provided separately from the first module and executes protocol control in compliance with a second interface standard; and
a third module that is provided for a physical layer shared between the first interface standard and the second interface standard, wherein the first module includes a first MAC (Media Access Layer) in conformity with an RMMI (Reference M-PHY Module Interface).
2. The interface circuit according to claim 1 , wherein the first interface standard is a UFS (Universal Flash Storage) standard, and the second interface standard is an M-PCIe (Mobile-Peripheral Component Interconnect Express) standard.
3. The interface circuit according to claim 1 , comprising a switch control unit that switches a destination for connection of the third module to the first module or the second module.
4. The interface circuit according to claim 1 , wherein the first module conforms to UniPro (Unified Protocol).
5. The interface circuit according to claim 1 , wherein the second module is provided for a transaction layer and a data link layer, and wherein the third module is provided for an M-PHY (Mobile-Physical Layer).
6. The interface circuit according to claim 1 further comprising:
a first pin that is intrinsic to the first interface standard; and
a second pin that is intrinsic to the second interface standard.
7. The interface circuit according to claim 6 , wherein the first interface standard is an M-PCIe (Mobile-Peripheral Component Interconnect Express) standard, and the second interface standard is a PCIe (Peripheral Component Interconnect Express) standard.
8. The interface circuit according to claim 7 , wherein the second module includes a second MAC in conformity with a PIPE (Physical Interface for PCI Express).
9. The interface circuit according to claim 6 , comprising a switch control unit that switches a destination for connection of the third module to the first module or the second module.
10. The interface circuit according to claim 6 , wherein the second module is provided for a transaction layer and a data link layer, and wherein the third module is provided for an M-PHY (Mobile-Physical Layer).
11. An interface circuit comprising:
a first module that executes protocol control in compliance with a first interface standard;
a second module that is provided separately from the first module and executes protocol control shared between a second interface standard and a third interface standard;
a third module that is provided for a physical layer shared between the first interface standard and the second interface standard; and
a fourth module that is provided separately from the third module and is provided for a physical layer in compliance with the third interface standard.
12. The interface circuit according to claim 11 , wherein the first interface standard is a UFS (Universal Flash Storage) standard, the second interface standard is an M-PCIe (Mobile-Peripheral Component Interconnect Express) standard, and the third interface standard is a PCIe (Peripheral Component Interconnect Express) standard.
13. The interface circuit according to claim 11 , comprising:
a first switch control unit that switches a destination for connection of the third module to the first module or the second module; and
a second switch control unit that switches a destination for connection of the second module to the third module or the fourth module.
14. The interface circuit according to claim 11 , wherein the first module conforms to UniPro.
15. The interface circuit according to claim 11 , wherein the second module is provided for a transaction layer and a data link layer.
16. The interface circuit according to claim 11 , wherein the third module is provided for an M-PHY, and wherein the fourth module is provided for a PCIe PHY.
17. The interface circuit according to claim 11 further comprising:
a first pin that is intrinsic to the first interface standard; and
a second pin that is intrinsic to the second interface standard; and
a third pin that is intrinsic to the third interface standard.