Semiconductor device

1. A semiconductor device, comprising:

stacked M semiconductor chips, M being an integer of 2 or more;

electrodes that are provided in the semiconductor chips to electrically connect the semiconductor chips in a direction of stacking; and

transmission units that are provided for the semiconductor chips and, based on a chip identification information of a semiconductor chip in a present stage, transmit the chip identification information to a semiconductor chip in a next stage through the electrodes, or transmit a data for setting the chip identification information, wherein

a direction in which an external signal is sent through the electrodes is opposite to a direction in which the chip identification information is transmitted through the electrodes,

the external signal is outputted to the semiconductor chips, and

the chip identification information is outputted from the semiconductor chips,

wherein, at a corresponding transmission unit, the semiconductor chip in the present stage counts up its chip identification information upon detection of power-on and then transmits it to the semiconductor chip in the next stage,

wherein a number of electrodes equal to or more than a number of bits by which the semiconductor chips can be identified are provided for each of the semiconductor chips,

wherein the corresponding transmission unit inverts bit information corresponding to an electrode in N-th stage according to transmission of bit information for 2 N-1 layers between the semiconductor chips, N being an integer of 2 or more,

wherein the corresponding transmission unit includes a decode unit that, based on first bit information sent from a semiconductor chip in a previous stage to an electrode in the previous stage of the semiconductor chip in the present stage and second bit information sent from the semiconductor chip in the previous stage to an electrode in the present stage of the semiconductor chip in the present stage, generates third bit information to be sent to the electrode in the present stage of the semiconductor chip in the next stage,

wherein the decode unit includes

an EXOR circuit that generates the third bit information based on an exclusive OR of the first bit information and the second bit information, and

a drive circuit that sets the second bit information to a reset state upon detection of power-off,

wherein the drive circuit cancels the reset state upon detection of power-on and transmits the second bit information, and

wherein drive circuit includes

a NAND circuit that generates the second bit information based on a negative AND of the third bit information and a power-on detection signal, and

a MOS transistor that, when an output from the NAND circuit is applied to a gate, pulls down an input potential of the NAND circuit into which the third bit information is input.

2. The semiconductor device according to claim 1 , wherein, at the corresponding transmission unit, the semiconductor chip in the present stage resets its chip identification information upon detection of power-off.

3. The semiconductor device according to claim 1 , comprising a register that is provided for each of the semiconductor chips to hold the chip identification information of the semiconductor chip in the present stage.

4. The semiconductor device according to claim 1 , comprising a control unit that is provided for each of the semiconductor chips to identify in which layer the semiconductor chip in the present stage resides based on the chip identification information.

5. The semiconductor device according to claim 1 , comprising a controller that inputs the external signal into the semiconductor chips, wherein

the external signal is any one of an address latch enable signal, a command latch enable signal, a read enable signal, a write enable signal, a data signal, a data strobe signal, a chip enable signal, a write protect signal, a ready/busy signal, or a chip address, and

the chip identification information is outputted from the semiconductor chips to the controller.