Group write technique for a bus interface system
Embodiments of bus interface systems and methods of operating the same are disclosed. In one embodiment, a bus interface system includes a master bus controller and multiple slave bus controllers that are each coupled to a bus line. The master bus controller is configured to generate a first set of data pulses along the bus line representing a payload segment. Each of the slave bus controllers decodes the first set of data pulses along the bus line representing the payload segment and performs an error check. Each slave bus controller is then configured to generate an acknowledgement pulse along the bus line to indicate that the slave bus controller's particular error check was passed. In this manner, the bus interface system can perform a group write bus function and the master bus controller can determine that the multiple slave bus controllers each received an accurate copy of the payload segment.
1. A slave bus controller comprising:
a data demodulator configured to:
decode a first set of data pulses representing a payload segment into a decoded payload segment; and
perform a first error check on the decoded payload segment; and
an acknowledgment generator configured to be triggered to generate an acknowledgement signal by a trigger pulse, which is generated by another slave bus controller in response to an error check of a decoded payload segment decoded from the first set of data pulses representing the payload segment, and to generate the acknowledgement signal so that the acknowledgement signal indicates whether the decoded payload segment passed the first error check.
2. The slave bus controller of claim 1 wherein the acknowledgement generator is configured to generate an acknowledgment pulse in the acknowledgement signal so that the acknowledgement signal indicates that the decoded payload segment passed the first error check.
3. The slave bus controller of claim 1 wherein the data demodulator is further configured to:
decode a second set of data pulses representing a first error code into a decoded error code;
generate a second error code based on the decoded payload segment; and
perform the first error check on the decoded payload segment by comparing the decoded error code and the second error code.
4. The slave bus controller of claim 3 wherein the data demodulator is configured to generate the second error code based on the decoded payload segment by being configured to implement a first CRC algorithm on the decoded payload segment so as to generate the second error code as a second CRC.
5. The slave bus controller of claim 1 wherein the data demodulator is further configured to decode the first set of data pulses in accordance with a PWM bus protocol.
6. A bus interface system comprising:
a bus line;
a master bus controller coupled to the bus line wherein the master bus controller is configured to generate a first set of data pulses along the bus line representing a payload segment;
a first slave bus controller coupled to the bus line, wherein the first slave bus controller is configured to:
decode the first set of data pulses representing the payload segment into a first decoded payload segment;
perform a first error check on the first decoded payload segment; and
generate a first acknowledgment pulse along the bus line in response to the first decoded payload segment passing the first error check; and
a second slave bus controller coupled to the bus line, wherein the second slave bus controller is configured to
decode the first set of data pulses representing the payload segment into a second decoded payload segment;
perform a second error check on the second decoded payload segment; and
generate a second acknowledgment pulse along the bus line in response to the first acknowledgement pulse generated by the first slave bus controller.
7. The bus interface system of claim 6 wherein the first slave bus controller does not generate the first acknowledgment pulse when the first decoded payload segment fails the first error check.
8. The bus interface system of claim 7 wherein:
the master bus controller is configured to generate a first trigger pulse along the bus line when the first slave bus controller does not generate the first acknowledgment pulse; and
the second slave bus controller is configured to be triggered to generate the second acknowledgment pulse along the bus line by the first trigger pulse from the master bus controller.
9. The bus interface system of claim 6 wherein:
the first slave bus controller comprises a first memory device configured to store a first slave data image, wherein the first slave bus controller is further configured to store the first decoded payload segment within the first slave data in response to the first decoded payload segment passing the first error check; and
the second slave bus controller comprises a second memory device configured to store a second slave data, wherein the second slave bus controller is further configured to store the second decoded payload segment within the second slave data in response to the second decoded payload segment passing the second error check.
10. The bus interface system of claim 9 wherein the master bus controller comprises a third memory device configured to store a first slave data image and a second slave data image, wherein the master bus controller is configured to store the payload segment within the first slave data image in response to the first acknowledgement pulse and store the payload segment within the second slave data image in response to the second acknowledgement pulse.
11. The bus interface system of claim 6 wherein:
the master bus controller is further configured to:
generate a first error code based on the payload segment; and
generate a second set of data pulses along the bus line representing the first error code; and
the first slave bus controller is further configured to:
generate a second error code based on the first decoded payload segment;
decode the second set of data pulses representing the first error code into a first decoded error code; and
perform the first error check on the first decoded payload segment by comparing the first decoded error code and the second error code.
12. The bus interface system of claim 11 wherein the second slave bus controller is further configured to:
generate a third error code based on the second decoded payload segment;
decode the second set of data pulses representing the first error code into a second decoded error code; and
perform the second error check on the first decoded payload segment by comparing the second decoded error code and the third error code.
13. The bus interface system of claim 6 wherein:
the master bus controller is configured to generate the first set of data pulses along the bus line representing the payload segment in accordance with a pulse width modulation (PWM) bus protocol; and
the first slave bus controller and the second slave bus controller are configured to decode the first set of data pulses in accordance with the PWM bus protocol.
14. A method of operating a master bus controller, a first slave bus controller, and a second slave bus controller coupled along a bus line, comprising:
generating a first set of data pulses along the bus line representing a payload segment with the master bus controller;
decoding the first set of data pulses representing the payload segment into a first decoded payload segment with the first slave bus controller;
performing a first error check on the first decoded payload segment with the first slave bus controller; and
generating a first acknowledgement pulse along the bus line in response to the first decoded payload segment passing the first error check with the first slave bus controller;
decoding the first set of data pulses representing the payload segment into a second decoded payload segment with the second slave bus controller;
performing a second error check on the second decoded payload segment with the second slave bus controller; and
generating a second acknowledgement pulse along the bus line in response to the first acknowledgement pulse generated by the first slave bus controller.
15. The method of claim 14 further comprising:
storing first slave data with a first memory device of the first slave bus controller, wherein the first slave data is assigned to first memory addresses; and
storing the first decoded payload segment at a first memory address of the first memory addresses in response to the first decoded payload segment passing the first error check;
storing second slave data with a second memory device of the second slave bus controller, wherein the second slave data is assigned to second memory addresses; and
storing the second decoded payload segment at a second memory address of the second memory addresses in response to the second decoded payload segment passing the second error check.
16. The method of claim 15 further comprising:
storing a first slave data image with a third memory device of the master bus controller wherein the first slave data image is assigned to third memory addresses such that the third memory addresses correspond to the first memory addresses of the first slave data; and
storing the payload segment within the first slave data image at a third memory address of the third memory addresses in response to the first acknowledgement pulse, wherein the third memory address of the third memory addresses corresponds to the first memory address of the first memory addresses;
storing a second slave data image with the third memory device of the master bus controller wherein the second slave data image is assigned to fourth memory addresses such that the fourth memory addresses correspond to the second memory addresses of the second slave data; and
storing the payload segment within the second slave data image at a fourth memory address of the fourth memory addresses in response to the second acknowledgement pulse, wherein the fourth memory address of the fourth memory addresses corresponds to the second memory address of the second memory addresses.
17. The method of claim 14 wherein the first set of data pulses are generated with the master bus controller in accordance with a pulse width modulation (PWM) protocol.
18. The method of claim 17 wherein the first slave bus controller decodes the first set of data pulses in accordance with the PWM protocol, and the second slave bus controller decodes the first set of data pulses in accordance with the PWM protocol.