Sigma-delta analog-to-digital converter

1. A sigma-delta (Σ-Δ) analog-to-digital (A/D) converter, comprising:

a summing stage, configured to receive an input signal and subtract a first feedback signal and a second feedback signal from the input signal to generate a difference signal;

a loop filter coupled to an output node of the summing stage, and configured to filter the difference signal;

a quantizer coupled to an output node of the loop filter, and configured to quantize the filtered difference signal to generate a quantized signal, and to generate an overload signal according to the filtered difference signal, wherein the overload signal indicates whether the filtered difference signal is overloaded and/or an overload amount of the filtered difference signal;

a first digital-to-analog (D/A) converter coupled to the quantizer to receive the quantized signal, and configured to generate the first feedback signal according to the quantized signal; and

a second D/A converter coupled to the quantizer to receive the overload signal, and configured to generate the second feedback signal according to the overload signal.

2. The sigma-delta A/D converter of claim 1 , wherein the quantizer has a first output node for outputting the quantized signal, and a second output node for outputting the overload signal.

3. The sigma-delta A/D converter of claim 1 , wherein the quantizer is further configured to compare the filtered difference signal and a predefined overload threshold, and generate the overload signal according to the comparison result of the filtered difference signal and the predefined overload threshold.

4. The sigma-delta A/D converter of claim 1 , further comprising:

a signal processing module, coupled between the quantizer and the first D/A converter, and configured to improve the linearity of the first feedback signal output by the first D/A converter.

5. The sigma-delta A/D converter of claim 4 , the signal processing module comprises a dynamic element matching module configured to transfer a mismatch in the quantized signal out of a passband of the loop filter.

6. The sigma-delta A/D converter of claim 4 , wherein the signal processing module comprises a compensation module for compensating an excess loop delay in the sigma-delta A/D converter.

7. The sigma-delta A/D converter of claim 1 , wherein the second D/A converter has a linearity lower than that of the first D/A converter.

8. The sigma-delta A/D converter of claim 1 , wherein the second D/A converter is a multi-level D/A converter.

9. The sigma-delta A/D converter of claim 1 , wherein the loop filter comprises cascaded integrators with feedback.

10. The sigma-delta A/D converter of claim 1 , wherein the loop filter is a resistor-inductor-capacitor network filter.

11. The sigma-delta A/D converter of claim 1 , further comprising:

a third D/A converter coupled to the quantizer to receive the quantized signal, and configured to generate a third feedback signal according to the quantized signal, and output the third feedback signal to an output node or an intermediate node of the loop filter.

12. The sigma-delta A/D converter of claim 1 , wherein the sigma-delta A/D converter is a continuous time sigma-delta A/D converter.