Clock generation apparatus, server system and clock control method

1. A clock generation apparatus, comprising: a clock determination unit which determines whether a cycle shift time between a first clock signal and a second clock signal satisfies a predetermined condition; and

a clock switching unit which switches said first clock signal and said second clock signal based on determination of said clock determination unit;

a clock bus to which an active system clock signal is outputted,

wherein said clock switching unit carries out switching so as to make one clock signal among said first clock signal and said second clock signal be said active system clock signal to be outputted to outside, and the other clock signal be a stand-by system clock signal to be restrained inside,

wherein said clock determination unit determines that a clock signal outputted to said clock bus can be switched when, as said predetermined condition, a first condition that said cycle shift time is equal to or more than a period from a setup start time to a hold end time of a signal specified for said clock bus and a second condition that said cycle shift time exists before a next setup start time are satisfied together.

2. The clock generation apparatus according to claim 1 , wherein a plurality of clock transmission circuits each having said clock determination unit and said clock switching unit are connected with each other via said clock bus.

3. The clock generation apparatus according to claim 2 , wherein said clock determination unit comprises:

a clock generating unit which generates a clock signal;

a clock measurement unit which measures a phase difference between said clock signal generated by its own clock transmission circuit and said active system clock signal; and

a clock switching availability determination unit determines, based on a phase difference between a clock signal having been generated by said own clock transmission circuit and measured by said clock measurement unit and said active system clock signal, that switching of a clock is possible when a cycle shift time between said clock signal generated by said own circuit and said active system clock signal satisfies said predetermined condition, wherein

said clock switching unit comprises:

a clock switching directing unit which issues, according to a clock switching request signal received from an upper system, an instruction to output a clock signal generated by said own clock transmission circuit based on determination by said clock switching availability determination unit; and

an output clock switching unit which carries out switching, according to said instruction of said clock switching directing unit, so as to make a clock signal generated by said own clock transmission circuit be outputted to said clock bus.

4. The clock generation apparatus according to claim 3 , wherein said clock switching directing unit of said clock transmission circuit having received said clock switching request signal

issues, according to said clock switching request signal, to said output clock switching unit of said own clock transmission circuit an instruction to make said clock transmission circuit outputting said active system clock signal suspend outputting a clock signal to said clock bus, and wherein

said output clock switching unit having received said clock switching request signal transmits, according to said instruction of said clock switching directing unit, to said output clock switching unit of said clock transmission circuit outputting said active system clock signal a clock output suspension signal to suspend outputting a clock signal to said clock bus.

5. The clock generation apparatus according to claim 3 , wherein said clock transmission circuit

comprises a clock phase changing unit which changes, upon being determined by said clock switching availability determination unit that said predetermined condition is not satisfied, a phase of a clock signal generated by said own clock transmission circuit so as to make said predetermined condition be satisfied.

6. A server system, comprising: a clock generation apparatus having a clock determination unit which determines whether a cycle shift time of a first clock signal and a second clock signal satisfies a predetermined condition or not and a clock switching unit which switches said first clock signal and said second clock signal based on determination of said clock determination unit;

a plurality of reception circuits to operate based on a clock signal outputted by said clock generation apparatus, said plurality of reception circuits being connected with said clock generation apparatus via a transmission line; and

a transmission line which connects said clock generation apparatus and said plurality of reception circuits, the transmission line to which an active system clock signal is outputted,

wherein said clock switching unit carries out switching so as to make one clock signal among said first clock signal and said second clock signal be said active system clock signal to be outputted to outside, and the other clock signal be a stand-by system clock signal to be restrained inside,

wherein said clock determination unit determines that a clock signal outputted to said clock bus can be switched when, as said predetermined condition, a first condition that said cycle shift time is equal to or more than a period from a setup start time to a hold end time of a signal specified for said clock bus and a second condition that said cycle shift time exits before a next setup start time are satisfied together.

7. A clock control method, comprising the steps of: determining whether a cycle shift time between a first clock signal and a second clock signal satisfies a predetermined condition or not; and

switching said first clock signal and said second clock signal based on determination of whether said cycle shift time satisfies said predetermined condition, wherein

determination that switching of a clock signal to be outputted to said clock bus is possible is made when, as said predetermined condition, a first condition that said cycle shift time is equal to or more than a period from a setup start time to a hold end time of a signal specified for said clock bus and a second condition that said cycle shift time exists before a next setup start time are satisfied together.