System and method for clock generation with an output fractional frequency divider
A system and a method generate clock signals using an output divider with modulus steps of half-integers (i.e., the output circuit includes a divider which divides by one or more of 2, 2.5, 3, 3.5, 4 . . . ).
1. A clock signal generation circuit, comprising:
a phase-locked loop including a voltage-controlled oscillator, the phase-locked loop receiving an input clock signal and providing an output signal that is phase-locked to the input clock signal; and
a frequency divider circuit receiving the output signal of the phase-locked loop, wherein the frequency divider circuit (i) generates a plurality of signals of various frequencies by dividing the frequency of the output signal of the phase-locked loop by selected numerical constants, and (ii) generates an output signal of the clock signal generation circuit from one of the signals of various frequencies, wherein the various frequencies include both an integer submultiple and a fractional submultiple of the frequency of the output signal of the phase-locked loop, and wherein the fractional submultiple is not an integer submultiple.
2. The clock signal generation circuit of claim 1 , wherein the frequency divider circuit comprises a first divider circuit and a second divider circuit connected in series, wherein the first divider circuit divides the frequency of the output signal of the phase-locked loop by a multiple of ½ that is greater than 1.
3. A method for generating a divided clock signal with a frequency that is a fractional submultiple of the frequency of an input clock signal, comprising:
using a phase-locked loop that includes a voltage-controlled oscillator and which receives the input clock signal and provides as output a reference clock signal, the reference clock signal being phase-locked to the input clock signal; and
in a frequency divider circuit that receives the reference clock signal as input, (i) generating a plurality of signals of various frequencies generated in the frequency divider circuit by dividing the reference clock signal by selected numerical constants, and (ii) generating the divided clock signal from one of the signals of various frequencies, wherein the various frequencies include both an integer submultiple and a fractional submultiple of the frequency of the reference clock signal, and wherein the fractional submultiple is not an integer submultiple.
4. The method of claim 3 , wherein the frequency divider circuit comprises a first divider circuit and a second divider circuit connected in series, wherein the first divider circuit divides the frequency of the reference signal by a multiple of ½ that is greater than 1.
5. The clock signal generation circuit of claim 1 , wherein the signals of various frequencies are each generated using a state machine.
6. The method of claim 3 , wherein the signals of various frequencies are each generated using a state machine.