Semiconductor device

1. A semiconductor device, comprising:

a memory string including a source selection transistor, first dummy memory cells, memory cells, second dummy memory cells and a drain selection transistor all coupled between a bit line and a common source line, and the drain selection transistor, the memory cells and the source selection transistor configured to operate, respectively, in response to voltages applied to a source selection line, first dummy word lines, word lines, second dummy word lines and a drain selection line, wherein the first dummy memory cells are coupled between the source selection transistor and the memory cells, and the second dummy memory cells are coupled between the drain selection transistor and the memory cells; and

an operation circuit configured for performing a program operation on the memory string,

wherein the operation circuit, after performing an operation programming the first and second dummy memory cells, is configured for sequentially performing a first operation programming memory cells adjacent to the drain selection transistor, a second operation programming memory cells adjacent to the source selection transistor, and a third operation programming remaining memory cells.

2. The semiconductor device of claim 1 ,

wherein the operation circuit is configured for performing the first operation before the second operation, and for performing the second operation before the third operation,

wherein the memory cells adjacent to the drain selection transistor are sequentially programmed by the first operation, and

wherein the operation circuit is configured to perform a read operation and a verify operation on the memory string.

3. The semiconductor device of claim 1 , wherein the operation circuit is configured for sequentially programming the memory cells in ascending order of distance from the drain selection transistor during the first operation.

4. The semiconductor device of claim 1 , wherein the operation circuit is configured for sequentially programming the memory cells in ascending order of distance from the source selection transistor during the second operation.

5. The semiconductor device of claim 1 , wherein the operation circuit is configured for sequentially programming the remaining memory cells in ascending order of distance from the source selection transistor during the third operation.

6. The semiconductor device of claim 1 , wherein the operation circuit is configured for sequentially programming the remaining memory cells in descending order of distance from the drain selection transistor during the third operation.

7. The semiconductor device of claim 1 , further comprising a pipe transistor coupled between intermediate memory cells, among the memory cells.

8. The semiconductor device of claim 1 , wherein the operation circuit is configured for programming the first and second dummy memory cells at substantially the same time.

9. The semiconductor device of claim 2 , wherein the operation circuit is configured for performing the read operation and the verify operation in the same order as the program operation.

10. A semiconductor device, comprising:

a source selection transistor coupled to a common source line located over a substrate;

a drain selection transistor coupled to a bit line located over the substrate;

a pipe transistor formed on the substrate;

a first cell string including memory cells coupled to the drain selection transistor;

a second cell string including memory cells coupled to the source selection transistor;

a third cell string including memory cells coupled between the second cell string and the pipe transistor;

a fourth cell string including memory cells coupled between the first cell string and the pipe transistor;

first dummy memory cells coupled between the source selection transistor and the second cell string;

second dummy memory cells coupled between the drain selection transistor and the first cell string; and

an operation circuit configured for performing a program operation on the memory cells included in the first to fourth cell strings,

wherein the operation circuit is configured for sequentially performing the program operations on the first to fourth cell strings after performing a program operation on the first and second dummy memory cells.

11. The semiconductor device of claim 10 , wherein the operation circuit is configured for sequentially programming the memory cells in ascending order of distance from the drain selection transistor when performing the program operation on the first cell string.

12. The semiconductor device of claim 10 , wherein the operation circuit is configured for programming the memory cells in ascending order of distance from the source selection transistor when performing the program operation on the second cell string.

13. The semiconductor device of claim 10 , wherein the operation circuit is configured for programming the memory cells in ascending order of distance from the source selection transistor when performing the program operation on the third cell string.

14. The semiconductor device of claim 10 , wherein the operation circuit is configured for programming the memory cells in descending order of distance from the drain selection transistor when performing the program operation on the fourth cell string.

15. The semiconductor device of claim 10 , wherein the operation circuit is configured for substantially simultaneously programming the first and second dummy memory cells.

16. The semiconductor device of claim 10 ,

wherein the operation circuit is configured to perform a read operation and a verify operation on the memory cells included in the first to fourth cell strings, and

wherein the operation circuit is configured for performing the read operation on the first to fourth cell strings in a sequential manner and the verify operation on the first to fourth cell strings in a sequential manner.