Method for testing a CMOS transistor
View Patent ↗A method for testing a CMOS transistor with an electrical testing unit, the CMOS transistor being formed in a semiconductor substrate of a semiconductor wafer. A plurality of CMOS transistors are formed on the semiconductor wafer and the electrical testing unit has a support plate and a metal layer formed on the support plate. The CMOS transistor having a first terminal contact, a second terminal contact and a third terminal contact, the second terminal contact configured as an electrically open control contact and in a process step the metal layer is positioned above the semiconductor wafer over the control contact and a potential difference between the first terminal contact and a third terminal contact is generated. The control contact is capacitively coupled by applying a drive potential to the metal layer, and the function of the CMOS transistor is tested by measuring an electrical variable dependent on the capacitive coupling.
1. A method for testing a CMOS transistor with an electrical testing unit, the method comprising:
forming the CMOS transistor in a semiconductor substrate of a semiconductor wafer, the CMOS transistor having a first terminal contact and a second terminal contact and a third terminal contact, the second terminal contact being configured as an electrically open control contact, wherein at least two CMOS transistors are formed on the semiconductor wafer;
providing the electrical testing unit with a support plate;
forming a conductive layer on the support plate;
positioning the conductive layer above the semiconductor wafer over the control contact;
generating a potential difference between the first terminal contact and a third terminal contact;
capacitively coupling the control contact to the electrical testing unit by applying a drive potential to the conductive layer to test the CMOS transistor; and
testing a function of the CMOS transistor by measuring an electrical variable dependent on the capacitive coupling.
2. The method for testing a CMOS transistor according to claim 1 , wherein a value of the drive potential is varied to obtain a characteristic of the electrical variable.
3. The method for testing a CMOS transistor according to claim 1 , wherein the drive potential is varied within a range from minus twenty volts to plus twenty volts.
4. The method for testing a CMOS transistor according to claim 3 , wherein the drive potential is varied in 5-volt steps.
5. The method for testing a CMOS transistor according to claim 1 , wherein the third terminal contact is connected to a ground potential.
6. The method for testing a CMOS transistor according to claim 1 , wherein a current flow between the first terminal contact and the third terminal contact or a voltage at an output terminal connected to the first terminal contact is measured as the electrical variable.
7. The method for testing a CMOS transistor according to claim 1 , wherein the support plate has a ceramic connection.
8. The method for testing a CMOS transistor according to claim 1 , wherein the electrical testing unit comprises a probe card, and wherein the first terminal contact is contacted via the probe card and supplied with a voltage.
9. The method for testing a CMOS transistor according to claim 1 , wherein, for contacting the CMOS transistor, the probes of the probe card are passed through openings in the support plate.
10. The method for testing a CMOS transistor according to claim 1 , wherein the conductive layer comprises titanium and/or silver and is made in the shape of a trace.
11. The method for testing a CMOS transistor according to claim 1 , wherein the support plate is smaller than 6 cm 2 in size, and wherein the conductive layer on the support plate comprises less than 70% of the area of the support plate.
12. The method for testing a CMOS transistor according to claim 1 , wherein the CMOS transistor is made as a gas-sensitive SGFET or gas-sensitive CCFET, wherein the second terminal contact comprises a plate-shaped metal surface, and wherein the conductive layer is positioned above the metal surface.
13. The method for testing a CMOS transistor according to claim 1 , wherein the electrical testing unit includes three electrically-conducting probes that extend from a probe holder through the support plate and the conductive layer to a surface of one of the CMOS transistors.
14. The method for testing a CMOS transistor according to claim 13 , further comprising the step of:
moving the electrical testing unit over each of the CMOS transistors formed on the semiconductor wafer.
15. The method for testing a CMOS transistor according to claim 1 , wherein the potential difference between the first terminal contact and a third terminal contact is generated by applying voltage between the conductive layer and the third terminal contact, wherein the third terminal contact is the a source contact of the CMOS transistor.
16. The method for testing a CMOS transistor according to claim 1 , wherein a ratio between an output voltage at the first terminal contact and the drive potential applied to the conductive layer is measured to test the CMOS transistor.
17. A method for testing a CMOS transistor with an electrical testing unit, the method comprising:
forming the CMOS transistor in a semiconductor substrate of a semiconductor wafer, the CMOS transistor having a first terminal contact and a second terminal contact and a third terminal contact, the second terminal contact being configured as an electrically open control contact, wherein a plurality of CMOS transistors are formed on the semiconductor wafer;
providing the electrical testing unit with a support plate;
forming a conductive layer on the support plate;
positioning a conductive layer above the semiconductor wafer over the control contact;
generating a potential difference between the first terminal contact and a third terminal contact;
capacitively coupling the control contact by applying a drive potential to a conductive layer; and
testing a function of the CMOS transistor by measuring an electrical variable dependent on the capacitive coupling, wherein the support plate is smaller than 6 cm 2 in size, and wherein the conductive layer on the support plate comprises less than 70% of the area of the support plate.