VARIED SILICON RICHNESS SILICON NITRIDE FORMATION
A method, in one embodiment, can include forming a tunnel oxide layer on a substrate. In addition, the method can include depositing via atomic layer deposition a first layer of silicon nitride over the tunnel oxide layer. Note that the first layer of silicon nitride includes a first silicon richness. The method can also include depositing via atomic layer deposition a second layer of silicon nitride over the first layer of silicon nitride. The second layer of silicon nitride includes a second silicon richness that is different than the first silicon richness.
1 . An integrated circuit memory device comprising:
a substrate;
a tunnel oxide layer disposed over said substrate;
a first layer of silicon nitride disposed over said tunnel oxide layer via atomic layer deposition, said first layer of silicon nitride comprises a first silicon richness value; and
a second layer of silicon nitride disposed over said first layer of silicon nitride via atomic layer deposition, said second layer of silicon nitride comprises a second silicon richness value that is different than said first silicon richness value.
2 . The integrated circuit memory device of claim 1 , wherein said second silicon richness value is less than said first silicon richness value.
3 . The integrated circuit memory device of claim 1 , wherein said second silicon richness value is greater than said first silicon richness value.
4 . The integrated circuit memory device of claim 1 , wherein said substrate comprises silicon.
5 . The integrated circuit memory device of claim 1 , further comprising:
a third layer of silicon nitride disposed over said second layer of silicon nitride via atomic layer deposition, said third layer of silicon nitride comprises a third silicon richness value that is different than said second silicon richness value.
6 . The integrated circuit memory device of claim 5 , wherein said third silicon richness value is less than said second silicon richness value.
7 . The integrated circuit memory device of claim 5 , wherein said third silicon richness value is greater than said second silicon richness value.
8 . The integrated circuit memory device of claim 5 , wherein said third layer of silicon nitride comprises a stoichiometric silicon nitride film.
9 . An integrated circuit memory device comprising:
a substrate;
a tunnel oxide layer disposed over said substrate;
a first layer of silicon nitride disposed over said tunnel oxide layer via atomic layer deposition, said first layer of silicon nitride comprises a first silicon richness value; and
a second layer of silicon nitride disposed over said first layer of silicon nitride via atomic layer deposition, said second layer of silicon nitride comprises a second silicon richness value, the first silicon richness value is changed by a predefined amount to produce said second silicon richness value.
10 . The integrated circuit memory device of claim 9 , wherein said first layer of silicon nitride comprises a non-stoichiometric silicon nitride layer.
11 . The integrated circuit memory device of claim 10 , wherein said second layer of silicon nitride is in contact with said first layer of silicon nitride.
12 . The integrated circuit memory device of claim 9 , wherein said second layer of silicon nitride comprises a stoichiometric silicon nitride film.
13 . The integrated circuit memory device of claim 9 , further comprising:
a third layer of silicon nitride disposed over said second layer of silicon nitride via atomic layer deposition, said third layer of silicon nitride comprises a third silicon richness value, the second silicon richness value is changed by another predefined amount to produce said third silicon richness value.
14 . The integrated circuit memory device of claim 13 , wherein said first layer of silicon nitride comprises a non-stoichiometric silicon nitride layer.
15 . The integrated circuit memory device of claim 13 , wherein said third layer of silicon nitride is in contact with said second layer of silicon nitride.
16 . The integrated circuit memory device of claim 13 , wherein said third layer of silicon nitride comprises a stoichiometric silicon nitride film.
17 . An integrated circuit memory device comprising:
a substrate;
a tunnel oxide layer formed on said substrate;
a first non-stoichiometric silicon nitride layer disposed onto said tunnel oxide layer via a first atomic layer deposition, said a first non-stoichiometric silicon nitride layer comprises a first silicon richness value;
a first silicon nitride layer disposed above said first non-stoichiometric silicon nitride layer via a second atomic layer deposition, said first silicon nitride layer comprises a second silicon richness value, the first silicon richness value is reduced by a predefined amount to produce said second silicon richness value; and
a second silicon nitride layer disposed above said first silicon nitride layer via a third atomic layer deposition, said second silicon nitride layer comprises a third silicon richness value, the second silicon richness value is reduced by another predefined amount to produce said third silicon richness value.
18 . The integrated circuit memory device of claim 17 , wherein said first silicon nitride layer is in contact with said first non-stoichiometric silicon nitride layer.
19 . The integrated circuit memory device of claim 17 , wherein said second silicon nitride layer is in contact with said first silicon nitride layer.
20 . The integrated circuit memory device of claim 17 , wherein said second silicon nitride layer comprises an upper film of stoichiometric silicon nitride.