Level shift and inverter circuits for GaN devices
GaN-based half bridge power conversion circuits employ control, support and logic functions that are monolithically integrated on the same devices as the power transistors. In some embodiments a low side GaN device communicates through one or more level shift circuits with a high side GaN device. Both the high side and the low side devices may have one or more integrated control, support and logic functions. Some devices employ electro-static discharge circuits and features formed within the GaN-based devices to improve the reliability and performance of the half bridge power conversion circuits.
1. A level shift circuit comprising:
a first GaN-based inverter circuit comprising:
a first input terminal,
a first output terminal, and
a first inversion circuit coupled between the first input and the first output terminals and configured to receive a first input logic signal at the first input terminal and in response, provide a first inverted output logic signal at the first output terminal,
wherein the first input logic signal is generated with reference to a first power supply voltage, wherein the first inverted output logic signal is generated with reference to a second power supply voltage, and wherein the first power supply voltage is substantially DC and the second power supply voltage is from a floating power supply; and
a second GaN-based inverter circuit comprising:
a second input terminal,
a second output terminal, and
a second inversion circuit coupled between the second input terminal and the second output terminal and configured to receive a second input logic signal at the second input terminal and in response, provide a second inverted output logic signal at the second output terminal, wherein the second inversion circuit and the first inversion circuit are dissimilar,
wherein the second input logic signal is generated with reference to the first power supply voltage, wherein the second inverted output logic signal is generated with reference to the second power supply voltage, and
wherein the first inversion circuit and the second inversion circuit are integrated on a GaN based device.
2. The level shift circuit of claim 1 , wherein the second power supply voltage is more than 20 volts greater than the first power supply voltage.
3. The level shift circuit of claim 1 wherein the first inversion circuit comprises a first GaN-based enhancement-mode transistor having a gate coupled to the first input terminal, a drain coupled to the first output terminal, and a source coupled to the first power supply voltage.
4. The level shift circuit of claim 3 wherein the first inversion circuit further comprises a current sink device coupled between the source and the first power supply voltage.
5. The level shift circuit of claim 3 wherein the first inversion circuit further comprises a pull up device coupled between the drain and a floating power supply.
6. The level shift circuit of claim 1 wherein the first input logic signal controls on and off transitions of a high side gate.
7. The level shift circuit of claim 6 further comprising at least one logic gate configured to prevent simultaneous conduction of high and low side transistors.
8. The level shift circuit of claim 1 further comprising an active pull-up device configured to shorten a time required to reset the first inverted output logic signal to a positive state when the first input logic signal changes from a high state to a low state.
9. The level shift circuit of claim 1 having a first capacitance between the first output terminal and a floating voltage and a second capacitance between the first output terminal and ground, wherein the first capacitance is greater than the second capacitance.
10. The level shift circuit of claim 9 wherein an overvoltage condition on the first output terminal is prevented by a clamp.
11. The level shift circuit of claim 1 wherein a floating supply voltage signal is measured, and in response, a supply voltage logic signal is generated and combined with the first inverted output logic signal.
12. The level shift circuit of claim 11 wherein the supply voltage logic signal is coupled with a hysteretic inverter.
13. The level shift circuit of claim 1 , wherein the second inversion circuit comprises a second GaN-based enhancement-mode transistor having a gate coupled to the second input terminal, a drain coupled to the second output terminal, and a source coupled to the first power supply voltage.
14. The level shift circuit of claim 1 , wherein the first input logic signal is received from a level shift driver and the second input logic signal is received from a pulse generator.
15. The level shift circuit of claim 1 , wherein the second inverted output logic signal is transmitted to a circuit configured to prevent a change in the first inverted output logic signal.
16. An electronic power conversion component comprising:
a package base;
one or more GaN-based dies secured to the package base and comprising:
a first GaN-based inverter circuit comprising:
a first input terminal,
a first output terminal,
a first inversion circuit coupled between the first input and the first output terminals and configured to receive a first input logic signal at the first input terminal and in response, provide a first inverted output logic signal at the first output terminal,
wherein the first input logic signal is generated with reference to a first power supply voltage, wherein the first inverted output logic signal is generated with reference to a second power supply voltage, and wherein the first power supply voltage is substantially DC and the second power supply voltage is from a floating power supply; and
a second GaN-based inverter circuit comprising:
a second input terminal,
a second output terminal, and
a second inversion circuit coupled between the second input terminal and the second output terminal and configured to receive a second input logic signal at the second input terminal and in response, provide a second inverted output logic signal at the second output terminal, wherein the second inversion circuit and the first inversion circuit are dissimilar,
wherein the second input logic signal is generated with reference to the first power supply voltage, wherein the second inverted output logic signal is generated with reference to the second power supply voltage, and
wherein the first inversion circuit and the second inversion circuit are integrated on a GaN based device.
17. The power conversion component of claim 16 , wherein the second power supply voltage is more than 20 volts greater than the first power supply voltage.
18. The power conversion component of claim 16 wherein the first inversion circuit comprises a first GaN-based enhancement-mode transistor having a gate coupled to the first input terminal, a drain coupled to the first output terminal, and a source coupled to the first power supply voltage.
19. A method of operating GaN-based level shift circuit, the method comprising:
transmitting a first input logic signal to a first input terminal and in response, a first inversion circuit providing a first inverted output logic signal on a first output terminal to control a gate of a power transistor, wherein the first input logic signal is generated with reference to a first power supply voltage, wherein the first inverted output logic signal is generated with reference to a second power supply voltage, and wherein the first power supply voltage is substantially DC and the second power supply voltage is from a floating power supply; and
transmitting a second input logic signal to a second input terminal and in response, a second circuit providing a second output logic signal on a second output terminal to control the gate of the power transistor, wherein the second circuit and the first circuit are dissimilar, wherein the second input logic signal is generated with reference to the first power supply voltage, wherein the second output logic signal is generated with reference to the second power supply voltage,
wherein the first inversion circuit and the second inversion circuit are integrated on a GaN based device.